ac100 team mailing list archive

[Gordan Bobic <gordan@xxxxxxxxxx>]

board-paz00-power.c:

ldo2 controls vdd_aon

Both vdd_core and vdd_aon must be 50mV above the vdd_cpu. Therefore, 
they should be the same. This patch changes ldo2 upper limit to 1300mV 
in line with vdd_core.

tegra2_dvfs.c.patch

The maximum voltage in the cpu array is 1125, and this is used by some 
SKUs. However, the rail_vdd_cpu has .max_millivolts set to 1100. This is 
increaset to 1125 to be consistent with the entries in the CPU array.

Similarly, some SKUs have vdd_core limit defined to be 1300mV, but the 
vdd_core and vdd_aon rail limits are set to 1275. This patch adjusts 
them to 1300 to be consistent with the core_speedo_max array.

Note, however, that I am not sure what the point of having core limits 
this high is. If the core and aon always follow cpu voltages + 50mV, 
then the most they are ever going to be set to is 1125+50=1175mV. 
However, the nominal voltage is set to 1200mV, and that means that 
vdd_core never drops below 1200mV.

In light of that, should we change the core_speedo_max_millivolts as 
follows:

  static const int core_speedo_max_millivolts[NUM_SPEED_LEVELS] =
-         { 1225, 1225, 1300 };
+         { 1200, 1200, 1200 };


and

Adjust rail_vdd_core and rail_vdd_aon to have .max_millivolts = 1200 to 
match? Also, in that case, the initialization of the voltage regulators 
in board-paz00-power.c should set 1200 as the limit.

What are people's thoughts on this? This is not about OC-ing or 
under-volting, it is about making the values consistent across the board.

IMO the code that controls this is very messily designed - these limits 
should be settable in one place only, not in 3 as they are now. They 
should be inferred from the speedo_max_millivolts arrays and the 
initialization limits and rail_vdd structs set implicitly. But changing 
all that is possibly a step further than I imagine the current 
maintainers would be willing to entertain, especially since the 
messiness is coming from the upstream nvidia kernel.

Gordan

diff --git a/arch/arm/mach-tegra/board-paz00-power.c b/arch/arm/mach-tegra/board-paz00-power.c
index 000b32b..5fe1d78 100644
--- a/arch/arm/mach-tegra/board-paz00-power.c
+++ b/arch/arm/mach-tegra/board-paz00-power.c
@@ -132,7 +132,7 @@ static struct regulator_init_data sm1_data  = REGULATOR_INIT(sm1,  725,  1125, t
 static struct regulator_init_data sm2_data  = REGULATOR_INIT(sm2,  3000, 3700, true);
 static struct regulator_init_data ldo0_data = REGULATOR_INIT(ldo0, 1250, 3300, false);
 static struct regulator_init_data ldo1_data = REGULATOR_INIT(ldo1, 725,  1100, true);
-static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725,  1275, false);
+static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725,  1300, false);
 static struct regulator_init_data ldo3_data = REGULATOR_INIT(ldo3, 1250, 3300, true);
 static struct regulator_init_data ldo4_data = REGULATOR_INIT(ldo4, 1700, 1800, true);
 static struct regulator_init_data ldo5_data = REGULATOR_INIT(ldo5, 1250, 2850, true);

diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c
index a8f968d..cf5e2ba 100644
--- a/arch/arm/mach-tegra/tegra2_dvfs.c
+++ b/arch/arm/mach-tegra/tegra2_dvfs.c
@@ -54,14 +54,14 @@ static const int core_speedo_max_millivolts[NUM_SPEED_LEVELS] =
 
 static struct dvfs_rail tegra2_dvfs_rail_vdd_cpu = {
 	.reg_id = "vdd_cpu",
-	.max_millivolts = 1100,
+	.max_millivolts = 1125,
 	.min_millivolts = 750,
 	.nominal_millivolts = 1100,
 };
 
 static struct dvfs_rail tegra2_dvfs_rail_vdd_core = {
 	.reg_id = "vdd_core",
-	.max_millivolts = 1275,
+	.max_millivolts = 1300,
 	.min_millivolts = 950,
 	.nominal_millivolts = 1200,
 	.step = 150, /* step vdd_core by 150 mV to allow vdd_aon to follow */
@@ -69,7 +69,7 @@ static struct dvfs_rail tegra2_dvfs_rail_vdd_core = {
 
 static struct dvfs_rail tegra2_dvfs_rail_vdd_aon = {
 	.reg_id = "vdd_aon",
-	.max_millivolts = 1275,
+	.max_millivolts = 1300,
 	.min_millivolts = 950,
 	.nominal_millivolts = 1200,
 #ifndef CONFIG_TEGRA_CORE_DVFS