desktop-packages team mailing list archive

[Chris J Arges <1401788@xxxxxxxxxxxxxxxxxx>]

Timo,

Can you fill out the an SRU justification to make it clear why this fix
needs to be SRUed? In addition I see three patches identified in
(https://bugs.freedesktop.org/show_bug.cgi?id=79053#c76) do all three
need to be backported?

** Description changed:

+ SRU Justification:
+ [Impact]
+ Users of hardware with affected Intel graphics can experience graphics issues.
+ 
+ [Test Case]
+ Run affected hardware and ensure it doesn't glitch.
+ 
+ [Fix]
+ 
  commit 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad
  Author: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
  Date:   Wed Nov 19 15:10:05 2014 +0200
  
-     sna: gen8 BLT broken when address has bit 4 set
-     
-     With bit 4 set in address, the gen8 blitter fails and blits errorneously
-     into the cacheline preceeding the destination and similarly when reading from
-     the source, corrupting memory.
-     
-     v2: Update the destination base offset pattern as revealed
-         by igt/tests/gem_userptr_blits/destination-bo-align
-     
-     v3: Check base address as well
-     
-     Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79053
+     sna: gen8 BLT broken when address has bit 4 set
+ 
+     With bit 4 set in address, the gen8 blitter fails and blits errorneously
+     into the cacheline preceeding the destination and similarly when reading from
+     the source, corrupting memory.
+ 
+     v2: Update the destination base offset pattern as revealed
+         by igt/tests/gem_userptr_blits/destination-bo-align
+ 
+     v3: Check base address as well
+ 
+     Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79053

** Description changed:

- SRU Justification:
- [Impact]
- Users of hardware with affected Intel graphics can experience graphics issues.
- 
- [Test Case]
- Run affected hardware and ensure it doesn't glitch.
- 
- [Fix]
- 
  commit 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad
  Author: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
  Date:   Wed Nov 19 15:10:05 2014 +0200
  
      sna: gen8 BLT broken when address has bit 4 set
  
      With bit 4 set in address, the gen8 blitter fails and blits errorneously
      into the cacheline preceeding the destination and similarly when reading from
      the source, corrupting memory.
  
      v2: Update the destination base offset pattern as revealed
          by igt/tests/gem_userptr_blits/destination-bo-align
  
      v3: Check base address as well
  
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79053

-- 
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Packages, which is subscribed to xserver-xorg-video-intel in Ubuntu.
https://bugs.launchpad.net/bugs/1401788

Title:
  backport BDW/CHV sna BLT fix

Status in X.org xf86-video-intel:
  Fix Released
Status in xserver-xorg-video-intel package in Ubuntu:
  Fix Released
Status in xserver-xorg-video-intel source package in Trusty:
  New
Status in xserver-xorg-video-intel source package in Utopic:
  New
Status in xserver-xorg-video-intel source package in Vivid:
  Fix Released

Bug description:
  commit 3a22b6f6d55a5b1e0a1c0a3d597996268ed439ad
  Author: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
  Date:   Wed Nov 19 15:10:05 2014 +0200

      sna: gen8 BLT broken when address has bit 4 set

      With bit 4 set in address, the gen8 blitter fails and blits errorneously
      into the cacheline preceeding the destination and similarly when reading from
      the source, corrupting memory.

      v2: Update the destination base offset pattern as revealed
          by igt/tests/gem_userptr_blits/destination-bo-align

      v3: Check base address as well

      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79053

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