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Re: JIT compile strangeness

 

On Mon, Feb 01, 2010 at 09:46:50PM +0000, Harish Narayanan wrote:
> On 01/02/2010 20:38, Anders Logg wrote:
> > Can anyone else check if you see this bug or if it is Harish-specific?
> > Kristian? Garth?
>
> I guess it is me-specific, but it is showing up and disappearing almost
> entirely at random. I'll present it once more when (if) I am able to
> narrow it down.
>
> Harish

ok, try adding something like

  print dir(module)

inside the function _extract_element_and_dofmap in jit.py in FFC.

That should give you some hint on what goes wrong.

--
Anders

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