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[Launchpad Bug Tracker <1484486@xxxxxxxxxxxxxxxxxx>]

This bug was fixed in the package linux - 4.2.0-10.11

---------------
linux (4.2.0-10.11) wily; urgency=low

  [ Andy Whitcroft ]

  * Release Tracking Bug
    - LP: #1495208
  * No change rebuild to avoid issues with leading zero bytes on
    internal module signing key.  (see launchpad bug 1494943)

  [ Ming Lei ]

  * [Config] SERIAL_8250_DW=y for arm64

  [ Upstream Kernel Changes ]

  * drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv
    code
    - LP: #1484486
  * drm/i915/gen8: Add infrastructure to initialize WA batch buffers
    - LP: #1484486
  * drm/i915/gen8: Re-order init pipe_control in lrc mode
    - LP: #1484486
  * drm/i915/gen8: Add WaDisableCtxRestoreArbitration workaround
    - LP: #1484486
  * drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch
    workaround
    - LP: #1484486
  * drm/i915: Bail out early if WA batch is not available for given Gen
    - LP: #1484486
  * drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround
    - LP: #1484486
  * drm/i915: Update WaFlushCoherentL3CacheLinesAtContextSwitch
    - LP: #1484486
  * drm/i915/gen9: Implement WaDisableKillLogic for gen 9
    - LP: #1484486
  * drm/i915: Enable WA batch buffers for Gen9
    - LP: #1484486
  * drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaround
    - LP: #1484486
  * drm/i915: Update wa_ctx_emit() macro as per kernel coding guidelines
    - LP: #1484486
  * drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch
    workaround
    - LP: #1484486
  * drm/i915/gen9: Add
    WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
    - LP: #1484486
  * drm/i915:skl: Add WaEnableGapsTsvCreditFix
    - LP: #1484486
  * drm/i915/skl: revert duplicated WaBarrierPerformanceFixDisable:skl
    - LP: #1484486
  * drm/i915/skl: Don't expose the top most plane on gen9 display
    - LP: #1484486
  * drm/i915/skl WaDisableSbeCacheDispatchPortSharing
    - LP: #1484486
  * drm/i915/skl: WaIgnoreDDIAStrap is forever, always init DDI A
    - LP: #1484486
  * drm/i915: reduce indent in i9xx_hpd_irq_handler
    - LP: #1484531
  * drm/i915: reduce duplicate conditions in i9xx_hpd_irq_handler
    - LP: #1484531
  * drm/i915: reduce indent in intel_hpd_irq_handler
    - LP: #1484531
  * drm/i915: group all hotplug related fields into a new struct in
    dev_priv
    - LP: #1484531
  * drm/i915: add for_each_hpd_pin to iterate over hotplug pins
    - LP: #1484531
  * drm/i915: simplify conditions for skipping the 2nd hpd loop iterations
    - LP: #1484531
  * drm/i915: put back the indent in intel_hpd_irq_handler
    - LP: #1484531
  * drm/i915: merge the two hpd loops in intel_hpd_irq_handler to one
    - LP: #1484531
  * drm/i915: simplify condition for digital port
    - LP: #1484531
  * drm/i915: abstract away platform specific parts from hpd handling
    - LP: #1484531
  * drm/i915: Handle HPD when it has actually occurred
    - LP: #1484531
  * drm/i915: Set power domain for DDI-E
    - LP: #1484531
  * drm/i915: Set alternate aux for DDI-E
    - LP: #1484531
  * drm/i915/skl: enable DDI-E hotplug
    - LP: #1484531
  * drm/i915/bxt: fix DDI PHY vswing scale value setting
    - LP: #1494163
  * drm/i915/skl: Buffer translation improvements
    - LP: #1494163
  * drm/i915: Per-DDI I_boost override
    - LP: #1494163
  * drm/i915: fix VBT parsing for SDVO child device mapping
    - LP: #1494163
  * drm/i915/bxt: edp1.4 Intermediate Freq support
    - LP: #1494163
  * drm/i915: fix link rates reported for SKL
    - LP: #1494163
  * drm/i915: Allow parsing of variable size child device entries from VBT
    - LP: #1494163
  * drm/i915/skl: Update DDI buffer translation programming.
    - LP: #1494163
  * drm/i915: Enable HDMI on DDI-E
    - LP: #1484531
  * drm/i915/skl: Enable DDI-E
    - LP: #1484531
  * drm/i915: eDP can be present on DDI-E
    - LP: #1484531
  * drm/i915/skl: Adding DDI_E power well domain
    - LP: #1484531
  * drm/i915: set CDCLK if DPLL0 enabled during resuming from S3
    - LP: #1490035
  * drm/i915: Split atomic wm update to pre and post variants
    - LP: #1493746
  * drm/i915/skl: Drop the preliminary_hw_support flag
    - LP: #1486868
  * drm/i915: set FDI translations to NULL on SKL
    - LP: #1494163

 -- Andy Whitcroft <apw@xxxxxxxxxxxxx>  Sun, 13 Sep 2015 11:32:02 +0100

** Changed in: linux (Ubuntu Wily)
       Status: Triaged => Fix Released

-- 
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https://bugs.launchpad.net/bugs/1484486

Title:
  [i915 gen8/gen9] Add workarounds to fix hang bugs etc

Status in linux package in Ubuntu:
  Fix Released
Status in linux source package in Vivid:
  Fix Released
Status in linux source package in Wily:
  Fix Released

Bug description:
  4.3 will have a bunch of workarounds to fix silicon bugs and other
  bugfixes that need to be backported to both vivid and wily. Some are
  for gen8 chips which also allow cherry-picking the gen9 ones.

   drm/i915/skl: WaIgnoreDDIAStrap is forever, always init DDI A
   drm/i915/skl WaDisableSbeCacheDispatchPortSharing
   drm/i915/skl: Don't expose the top most plane on gen9 display
   drm/i915/skl: revert duplicated WaBarrierPerformanceFixDisable:skl
   drm/i915:skl: Add WaEnableGapsTsvCreditFix
   drm/i915/gen9: Add WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
   drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround
   drm/i915: Update wa_ctx_emit() macro as per kernel coding guidelines
   drm/i915/gen9: Add WaDisableCtxRestoreArbitration workaround
   drm/i915: Enable WA batch buffers for Gen9
   drm/i915/gen9: Implement WaDisableKillLogic for gen 9
   drm/i915: Update WaFlushCoherentL3CacheLinesAtContextSwitch
   drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround
   drm/i915: Bail out early if WA batch is not available for given Gen
   drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround
   drm/i915/gen8: Add WaDisableCtxRestoreArbitration workaround
   drm/i915/gen8: Re-order init pipe_control in lrc mode
   drm/i915/gen8: Add infrastructure to initialize WA batch buffers
   drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code

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