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[Brad Figg <brad.figg@xxxxxxxxxxxxx>]

This bug is awaiting verification that the kernel in -proposed solves
the problem. Please test the kernel and update this bug with the
results. If the problem is solved, change the tag 'verification-needed-
trusty' to 'verification-done-trusty'.

If verification is not done by 5 working days from today, this fix will
be dropped from the source code, and this bug will be closed.

See https://wiki.ubuntu.com/Testing/EnableProposed for documentation how
to enable and use -proposed. Thank you!


** Tags added: verification-needed-trusty

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https://bugs.launchpad.net/bugs/1369633

Title:
  4k laptop eDP display not working on a dell precision m3800

Status in HWE Next Project:
  New
Status in “linux” package in Ubuntu:
  Fix Released
Status in “linux” source package in Trusty:
  Fix Committed

Bug description:
  Impact: Some new laptops with 4k screens are starting to use dp 1.2
  only feature of supporting 5.4ghz link rates over displayport which
  was not turned on until 3.15 even though the plumbing for it was
  (mostly) there.  This should only make more devices work since it has
  to advertise support for the feature in the dpcd. previously dp 1.2
  screens which needed 5.4ghz link rates were forced to use 2.7ghz
  instead, which would not provide enough bandwidth for some high
  resolution/high bandwidth screens. It only affects haswell for trusty,
  broadwell is handled through i915_bdw module which already as this fix
  and the fix was upstream in 3.15-rc1 so utopic is unaffected.

  Fix: Allow the 5.4ghz link rate over displayport.

  This has been tested on an affected OEM laptop with a 4K display that
  requires 5.4ghz link rate to light up (without it the display never
  turns on) as well as 2 other haswell machines to be sure it doesn't
  regress.

   [ 5.297037] [drm:intel_modeset_stage_output_state] [CONNECTOR:16:eDP-1] to [CRTC:5]
   [ 5.297038] [drm:intel_modeset_affected_pipes] set mode pipe masks: modeset: 1, prepare: 1, disable: 0
   [ 5.297040] [drm:connected_sink_compute_bpp] [CONNECTOR:16:eDP-1] checking for sink bpp constrains
   [ 5.297042] [drm:intel_dp_compute_config] DP link computation with max lane count 4 max bw 14 pixel clock 533250KHz
   [ 5.297045] [drm:intel_dp_compute_config] DP link bw 14 lane count 4 clock 540000 bpp 24
   [ 5.297046] [drm:intel_dp_compute_config] DP link bw required 1279800 available 1728000
   [ 5.297047] [drm:intel_modeset_pipe_config] plane bpp: 24, pipe bpp: 24, dithering: 0

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