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Re: Re: New file uploaded to kicad-devel


Hi Pat,

I tried kipy on my project, and it looks like it crashed. Would you 
like a copy of my project to play with? Here is the output:

frohro@frohro-d610:~/Araya Classes/Prop & Rad/DG8SAQ 
VNA/DG8SAQ-KL7NA-VNA$ ~/Projects/kipy/tools/checkproj.py

Checking 1 pages

Traceback (most recent call last):
File "/home/frohro/Projects/kipy/tools/checkproj.py", line 37, in <module>
sch = ParseSchematic(proj)
File "/home/frohro/Projects/kipy/kipy/parsesch/__init__.py", line 105, 
in __init__
pageparts, pagepartials = parsesheet(page, libdb, warnings)
File "/home/frohro/Projects/kipy/kipy/parsesch/graphics/parse.py", 
line 142, in parsesheet
graphobj = InternalParse(pageinfo.sheetname, pageinfo.sheetdata, 
pageinfo.timestamp, libdict, warnings)
File "/home/frohro/Projects/kipy/kipy/parsesch/graphics/parse.py", 
line 131, in __init__
self.dispatch(pageinfo.items, self)
File "/home/frohro/Projects/kipy/kipy/parsesch/graphics/schitems.py", 
line 53, in dispatch
dispatchdict[item.__class__](item, page)
"/home/frohro/Projects/kipy/kipy/parsesch/graphics/components.py", line 
139, in __init__
"/home/frohro/Projects/kipy/kipy/parsesch/graphics/components.py", line 
121, in setlibinfo
boundary = list(libpart.boundary(self.subpart, self.variant))
File "/home/frohro/Projects/kipy/kipy/fileobjs/lib/component.py", line 
127, in boundary
self._boundaries[dictindex] = min(xlist), min(ylist), max(xlist), 
ValueError: min() arg is an empty sequence
frohro@frohro-d610:~/Araya Classes/Prop & Rad/DG8S

Hope this helps.


Patrick wrote:
> >
> > --- In kicad-devel@xxxxxxxxxxxxxxx 
> <mailto:kicad-devel%40yahoogroups.com>, kicad-devel@xxxxxxxxxxxxxxx 
> <mailto:kicad-devel%40yahoogroups.com> wrote:
> >
> > > File : /pompa.tar.gz
> > > Uploaded by : lomarcan77 <lomarcan@>
> > > Description : Test case for wrong netlist generation. Can also be 
> published as an example for strictly non-commercial usage
> >
> > OK this is my test case. As an example is not to be took to 
> seriously altought it is of production quality:P it is meant to be a 
> throw-away proof-of-concept board. The 'strange' component choice (and 
> the mix of THT and SMD one) is because it's designed to be built with 
> the component I have at hand in the workshop at work I.E. a >10A 
> mosfet is NOT the usual choice driving a 3-4A load:D:D
> I have updated my checkproj.py available for download at kipy.org, to 
> read in and validate the .net file output from eeschema against the 
> .sch/.lib files.
> It confirms that (according to my independently developed python 
> script), your "good" netlist was good and your "bad" netlist is bad.
> IMHO this is a better check on the .net output from eeschema than just 
> eyeballing the result and saying "yep, D2 is still not hooked up right."
> Please feel free to download this software and try it out. If you use 
> it on a regular basis, it will give you an independent check on the 
> validity of the kicad schematic.
> The only problem is that I parse special characters in net names a bit 
> differently than kicad, so it will report a difference in net names on 
> some nets with special characters. You can ignore these messages. I 
> will eventually try to fix it. (It doesn't see any such special 
> characters in the schematic you provided, but does on some of the demo 
> projects bundled with kicad.)
> I think the script works fine with Python 2.5 and 2.6, but it will 
> need some tweaking to work under Windows.
> Best regards,
> Pat

Rob Frohne, Ph.D., P.E.
E.F. Cross School of Engineering
Walla Walla University
100 SW 4th Street
College Place, WA 99324
(509) 527-2075	http://people.wallawalla.edu/~rob.frohne

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