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Proposal for the courtyard/assembly layer issue


Today I have tought about the problem. Courtyard is essentially only
a kind of bounding box. So it could be simply stored as an attribute,
instead of using a new layer. So we just add a tool in the module editor
(like the 'place anchor' one) to set this bounding box.

Display would be done with the package and a new checkbox in the
'render' tab (something like the 'render pads'). This because it's
actually useful only during component placement (to be really cheap we
could tie display to the 'component placement mode' switch, without
adding an entry to the 'render' tab). And since it's just a package
attribute it would be readily available to the DRC or whatever.

To go all the way we could (as a second step) include a fully developed
'assembly' pair (which would contain high resolution, non-trimmed silk
drawings and whatever it was needed). That would containing the package
reference and maybe value too...

My current workflow for preparing gerbers is as follow:

1) Standard gerber plots, drill and reports for the PCB and silk base.
References for small/unimportant component were already hidden.

2) Clip this silk with the solder mask to obtain the actual silkscreen
(I use gerbertool, do you know a free tool which does this?)

Please note that silk screen in machine mounted boards has a different
function than in hand mounted ones... we use it mostly for labelling
end-user features like fuses and connectors or maybe components for
aftermarket installation (almost all of our boards are selectively
depopulated...); hand mounted component (the less, the better because
it costs:D) are mounted following the assembly drawing *not* the silk
screen (of course, if it is there, they are happier). For some board we
don't apply silk at all (it can be a 10-20% discount on the board!)

Comment is actually not sent to them because contains design comment
(like keep out areas for bluetooth antennas), not fabrication ones
(which are in the drawing layer).

3) The above files are sent to the fabricator for panelization and
production. The drawing layer contains special annotations, like copper
weight, special milling operations, scoring and so on.

4) Silkscreen plot, removing values and forcing invisible text (to have
all the references); I don't need values on the assembly because they
follow the BOM; of course someone could like them, too.

5) Hack the apertures in the header with a script to have all readable
(minimum silk feature size for our process is 0,2 mm, obviously a 0603
designator would be a blob) and send it to the assembler with the pick
and place file (and the whole pcb documentation).

The board fabricator then send the panel files to the assembler to build
the complete panel program; about a month later I get the circuits ready

The morale is: 1) a flexible plot specification could be useful and 2)
in the same way some people could use an assembly layer feature (I
personally don't need it but others cad do have this feature).


Lorenzo Marcantonio
Logos Srl

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