kicad-developers team mailing list archive

[Lorenzo Marcantonio <l.marcantonio@xxxxxxxxxxxx>]

As requested, here is the explanation for thermal patterns for pads with holes, following the IPC-2222 standard (i.e. 'common' PCBs, not flex or HDI ones). Even if not directly implemented it's useful as a design guideline.

It's interesting that for the standard thermals only applies to THT pads: no thermal is assumed for SMD ones (probably because of the different technology for assembly: in fact patterns for wave-soldered SMDs are different from these for reflow assembly).

Citing IPC-2222, section 9.1.2 Thermal Relief in Conductor Planes ('web' is the spoke section of the thermal pattern):

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The relationship between the hole size, land and web area is critical. Typically, divide 60% of the minimum land area diameter by the number of webs desired to obtain the width of each web in accordance with the following example:

A. Land Size Calculation

[omissis, for now read it as 'pad diameter' for a 1.0 mm hole pad in the example]

Minimum land size = 1.35 mm diameter

B. Thermal Relief Calculation

Total Thermal Width = 60% of land size
  = 0.6 x 1.35 mm = 0.8 mm

C. Original Web Size Calculation

[omissis obvious calculation for 2- and 3-spokes pattern]

4-web width = 1/4 of total thermal width
  = 0.25 x 0.8 mm = 0.22 mm

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So, in a pinch, the 'basic' computation is just the 15% of the pad diameter (60% / 4 spokes). Also the antipad is substantially the area clearance, with a minimum of 0,25 for fabrication allowance (i.e. drill wandering).

There is then a somehow optional rule (i.e. I think nobody follows it):

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If the actual land diameter chosen is greater than the minimum value calculated, the percentage difference between the land diameters must be subtracted from the [total] web width calculation
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Obviously nobody follows it because *everybody* oversizes pads: the minimum pad diameter is hole + 0.10 (for the annulus) + 0.25 (fabrication allowance); this is often nearly-unsolderable (a 1.1 mm hole in only a 1.4 pad -- rounded up -- woul be rejected by most sane soldering operators).

At last, there are some constraint (some of them obvious):

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Total cumulative copper web for all layers in any plated-through hole should not exceed 4.0 mm for 1 oz copper or 2.0 mm for 2 oz copper
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I think this is a empirical guideline for total thermal dissipation to avoid unsolderability...

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The total of the thermal relief cross-sectional area divided by the number of planes connected to the plated through hole *shall* [emph. in original] not violate current carrying capacity requirements for a given hole.
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Obviously there should be enough current for the copper... so in an automatic computation I'd use the user-specified spoke width as a *minimum* spoke width to use: the designer obviusly knows what kind of current flows in that net (BTW current capacity is something everything-but-not-easy to compute, there is a full IPC standard dedicated to it)

And, I would add, spoke width must be at least of the minimum track size...

For the implementation sadly I'm now to busy to work as a kicad user than as a developer... however I've identified the CreateThermalReliefPadPolygon function in board_items_to_polygon_shape_transform.cpp: inserting the computation between the ones for aThermalGap and aCopperThickness should do the trick i.e. recomputing the aCopperThickness using the 15% rule and then proceeding with the other checks. If it wasn't for the UI it would be a one-liner patch.

In the same way the 'thermal for THT solid for SMD' option would be implemented in the ZONE_CONTAINER::AddClearanceAreasPolygonsToPolysList (BTW there are both boost and kpoly versions??? I'd hope one is dead code). I'd add another 'check-or-continue' test just before the item_boundingbox computation, near the CreateThermalReliefPadPolygon call (the pad struct is just there to check its type:D).

As before it's more a UI modification than a code one (and I have *no idea* on how to touch kicad's UI)

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Lorenzo Marcantonio
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