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Re: Clearance and rounding in kicad-nano

 

It seems like an important issue, do you know why is it happening exactly
or could you trace it?,

I think about it, and it shouldn't happen as you are working in mm (which
are multiple of the nm).....

hmmm


2012/6/20 Lorenzo Marcantonio <l.marcantonio@xxxxxxxxxxxx>

> I've got these issues when routing a board. Let's say I'm doing
> a 0,2/0,2mm routing (i.e. 0,2mm of track separated by 0,2mm of
> clearance). Which is huge by today standard (in mil it's about an 8/8)
> but the numbers are easy :D Grid is set to 0,05 as for IPC
> recommendations (also it's a good general purpose grid).
>
> Now, the issue is that you *can't* put the tracks at exactly the
> specified distance (DRC during track drawing rejects it). In fact, the
> 'stick to wall' feature (no better name for it, when you 'push' the track
> against another one) gives the following results:
>
>
> Po 0 30.8 15.9 30.8 20.1 0.2 -1
> De 15 0 1 4FE19D7F 0
> Po 0 31.200002 16.05 31.200002 20.100002 0.2 -1
> De 15 0 2 4FE19DC4 0
>
> Yes, that's 2 nanometers away :D these 2 nm anyway break the 'grid
> beauty' and are unconvenient anyway (you can't route adjacent tracks
> without the stick to wall feature).
>
> What's the plan for this? I suppose I could set the clearance to, say,
> 0,199998... I mean, there should be a better solution, IMHO
>
> --
> Lorenzo Marcantonio
> Logos Srl
>
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Miguel Angel Ajo Pelayo
http://www.nbee.es
+34 636 52 25 69
skype: ajoajoajo

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