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Message #12351
PATCH: export VRML and IDF maintenance
The attached patch:
1. adds S_POLYGON outlines to the VRML export; the demos interf_u and microwave now look prettier in the VRML export.
2. fixes a bug in idf_cylinder: '0' was not accepted as a valid board offset.
- Cirilo
=== modified file 'pcbnew/exporters/export_vrml.cpp'
--- pcbnew/exporters/export_vrml.cpp 2014-02-08 10:44:55 +0000
+++ pcbnew/exporters/export_vrml.cpp 2014-02-15 02:16:28 +0000
@@ -44,6 +44,7 @@
*
* 3. Export Graphics to Layer objects (see 3d_draw.cpp for clues) to ensure that custom
* tracks/fills/logos are rendered.
+ * module->TransformGraphicShapesWithClearanceToPolygonSet
*
* For mechanical correctness, we should use the following settings with arcs:
* 1. max. deviation: the number of edges should be determined by the max.
@@ -925,7 +926,8 @@
}
-static void export_vrml_edge_module( MODEL_VRML& aModel, EDGE_MODULE* aOutline )
+static void export_vrml_edge_module( MODEL_VRML& aModel, EDGE_MODULE* aOutline,
+ double aOrientation )
{
LAYER_NUM layer = aOutline->GetLayer();
double x = aOutline->GetStart().x * aModel.scale + aModel.tx;
@@ -936,6 +938,10 @@
switch( aOutline->GetShape() )
{
+ case S_SEGMENT:
+ export_vrml_line( aModel, layer, x, y, xf, yf, w );
+ break;
+
case S_ARC:
export_vrml_arc( aModel, layer, x, y, xf, yf, w, aOutline->GetAngle() / 10 );
break;
@@ -944,8 +950,41 @@
export_vrml_circle( aModel, layer, x, y, xf, yf, w );
break;
+ case S_POLYGON:
+ {
+ VRML_LAYER* vl;
+
+ if( !VRMLEXPORT::GetLayer( aModel, layer, &vl ) )
+ break;
+
+ int nvert = aOutline->GetPolyPoints().size();
+ int i = 0;
+
+ if( nvert < 3 ) break;
+
+ int seg = vl->NewContour();
+
+ if( seg < 0 )
+ break;
+
+ while( i < nvert )
+ {
+ CPolyPt corner( aOutline->GetPolyPoints()[i] );
+ RotatePoint( &corner.x, &corner.y, aOrientation );
+ corner.x += aOutline->GetPosition().x;
+ corner.y += aOutline->GetPosition().y;
+
+ x = corner.x * aModel.scale + aModel.tx;
+ y = - ( corner.y * aModel.scale + aModel.ty );
+ vl->AddVertex( seg, x, y );
+
+ ++i;
+ }
+ vl->EnsureWinding( seg, false );
+ }
+ break;
+
default:
- export_vrml_line( aModel, layer, x, y, xf, yf, w );
break;
}
}
@@ -1134,7 +1173,8 @@
break;
case PCB_MODULE_EDGE_T:
- export_vrml_edge_module( aModel, dynamic_cast<EDGE_MODULE*>( item ) );
+ export_vrml_edge_module( aModel, dynamic_cast<EDGE_MODULE*>( item ),
+ aModule->GetOrientation() );
break;
default:
=== modified file 'utils/idftools/idf_cylinder.cpp'
--- utils/idftools/idf_cylinder.cpp 2014-02-05 09:27:21 +0000
+++ utils/idftools/idf_cylinder.cpp 2014-02-15 02:11:13 +0000
@@ -177,7 +177,7 @@
tstr.clear();
tstr.str( line );
- if( (tstr >> extraZ) && extraZ > 0.0 )
+ if( (tstr >> extraZ) && extraZ >= 0.0 )
ok = true;
}
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