kicad-developers team mailing list archive

[Jean-Paul Louis <louijp@xxxxxxxxx>]

Guys,

I am reading all this thread, and I am amazed that people suggest a silk shape that will HAVE TO BE REMOVED by the PCB fabricator.
This is adding cost to a PCB without any value added.

The example shown by Lorenzo is a very good example. The yellow rectangle has zero value AND an extra cost, while just two lines (shown in white) provide the real value of locating the chip without hindering the manufacturing process.
On top to it, because it is just inside the guard area (outside rectangle), it provide guidance for the 
clearance between parts.

Thank you, Lorenzo.

Jean-Paul
AC9GH


On Jun 2, 2014, at 5:54 AM, Lorenzo Marcantonio <l.marcantonio@xxxxxxxxxxxx> wrote:

> On Mon, Jun 02, 2014 at 09:57:47AM +0200, Paweł Dras wrote:
>> IMHO some rules according to silk should be specified in convention. For
>> example line width should be the same (perhaps with some exceptions) in
> 
> IPC says that, depending on the environment, line should be 4/5/6 mils
> or 0.1/0.12/0.15 mm (yes, it depends on the 'main' unit). So for
> a nominal metric design it would be 0.12mm. However our fabricators says
> that silk is 0.2mm minimum anyway, since we usually do 'true' silk
> screening (not inkjet). YMMV, depending on the process available.
> 
>> whole library, because then the PCB looks clean and more "professional".
>> With pads over the silk is the same situation, in many cases after silk
>> erasure by solder mask it don't looks good on final product.
> 
> By experience after erasure it sucks a lot! SOICs with silk erasures
> seems jumbles of dots.
> 
>> Another problem is to wide placed silk.
>> For example in attachment is how looks now silk for 1206 resistor and my
>> proposal for new one. IMHO the silk should be tight to the pad, because
>> then when we place few such resistors close to each other we don't get a
>> mess with silk.
> 
> The new one is more like in principle to the IPC one (see attachment).
> The main issue is that silk for chip components eats valuable courtyard
> space, especially when you need a wider pad for probing (this is not
> taken in account by IPC!). In fact on the 0603 pads we use you can quite
> easily mount a 0805... As usual it depends on your target density.
> 
> See other attachment to see how do i do these usually (even the SOT23s
> are oversized for mechanical resistance). However I packed things way
> more than that, this is a test board designed for hand assembly :P
> 
>> I have a question, can be ref and value placed as in my attachment or
>> should  be above and below resistor?
> 
> Value usually is not shown on silk; it's already difficult enough to
> place the refdes! By convention refdes is on the placement point for
> fabrication drawing and... wherever it fits on the silk. If there is
> place, obviously... sometimes you see block of components (usually small
> passives) bracketed on the silk with the list of the references, but
> that is manual tune-up of the layout of course.
> 
> -- 
> Lorenzo Marcantonio
> Logos Srl
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