kicad-developers team mailing list archive

[Cirilo Bernardo <cirilo_bernardo@xxxxxxxxx>]

----- Original Message -----

> From: jp charras <jp.charras@xxxxxxxxxx>
> To: Cirilo Bernardo <cirilo_bernardo@xxxxxxxxx>; Ki Cad Developers <kicad-developers@xxxxxxxxxxxxxxxxxxx>
> Cc: 
> Sent: Monday, June 16, 2014 10:03 PM
> Subject: Re: [Kicad-developers] [PATCH] add feature and fix segfault in VRML exporter
> 
> Le 15/06/2014 08:55, Cirilo Bernardo a écrit :
> 
>>  I have put a new patch onto my github patch project:
>> 
>>  vrml_layer_pth.patch (https://github.com/cbernardo/kicad-patches)
>> 
>>  This patch adds more eyecandy to the VRML export but more importantly
>>  works around a potential segfault in the GLU tesselator. The patch
>>  incorporates the previous patch I posted which fixes some rendering
>>  glitches.
>> 
>>  The patch has been made against rev. 4942 and the VRML exporter and
>>  idf2vrml tool have been tested against all projects in the demo
>>  directory as well as existing private projects. There is a known
>>  visual glitch when plated holes intersect board edges and unplated
>>  board cutouts; this glitch can be seen in the pic_programmer demo
>>  project. Since plated holes intersecting board edges is a rare
>>  case (until castellated connectors become very popular) and this is
>>  purely a cosmetic feature, there are no current plans to improve on
>>  this.
>> 
>>  - Cirilo
> 
> Committed. Thanks.
> 



Thanks Jean-Pierre.  :)

- Cirilo