On Wed, Jul 16, 2014 at 10:33:06AM +0200, Maciej Sumiński wrote:
Are not they added as DRAWSEGMENTs on copper layers? I am willing to bet
that it is not handled by DRC.
I'm not accepting that bet :D
Why the track are not subclasses of segments is probably an old design
decision. Also because in that case arc tracks would need do be handled
(not that it would be a bad idea...)
In GAL editor you can have PCB edges in modules. There was not much code to
be added to handle this, unless I have forgotten about something. If you are
interested in details, have a look at commit 4987.1.84.
The old code also allowed this; is the rest of pcbnew that doesn't
collate pcb edges from modules with the ones in the board; an explicit
mechanism was added to the layer selector to *avoid* it being selectable
in the module editor.
Just another reason to have some kind of unified type for stuff in the
board and in the modules (IIRC another CERN proposal of not a lot of
time ago).
