With respect to text, the clearances for me would be vias (as holes
"corrupt" the text), component bodies, component pins, and any other
areas where soldermask is removed (implying a solder area or a
chassis/shield-to-PCB conduction area). I have not used or am not
aware of a "keepout all" area - but this would be another item in the
list of text clearance areas.
I would therefore not have a trace clearance for my boards. If there
is a use case for clearances from traces - then this starts to push
for some configuration to this otherwise atomic process.
For high-speed traces - one thought is that the material of a
silkscreen above the soldermask would somehow change impedance for the
traces unless the silkscreen was balanced across all paired signals.
So for users concerned about this effect - a trace vs. text check may
make sense. Most of my designs have no such slew rate or frequency
concerns and therefore no need for silkscreen keepouts for traces.
Even here - there is a subset of the total population of nets that
would "need" clearance.
Note: the primary purpose for this message is to outline some of the
high-level logic of what to check for text clearance and what should
perhaps be configurable including designation of a subset of nets.
Regards,
Jason
On Wed, Aug 13, 2014 at 11:52 AM, Wayne Stambaugh
<stambaughw@xxxxxxxxxxx <mailto:stambaughw@xxxxxxxxxxx>> wrote:
On 8/13/2014 12:00 PM, jp charras wrote:
> Le 13/08/2014 01:30, Simon Schumann a écrit :
>> Hello,
>>
>> here's a patch to tackle
https://bugs.launchpad.net/kicad/+bug/1201090
>>
>> It brings text checking on par with keepoutAreas (in fact I
used it as
>> template). At the moment boundary box is used as area to check
(per line
>> checking is being considered).
>>
>> It lacks pin checking (as well as keepoutAreas), but I will
send a patch
>> for both as soon as I figured out a nice way to do it.
>>
>>
>> I hope the patch is not too bad - it's my first one :)
>>
>> schuhumi
>
> Thanks, Simon.
>
> It was helpful.
> I modified it and added the drc pad test.
>
> The exact text shape is now used.
Just to make sure I'm understanding this correctly, I can place a
via or
trace inside the text bounding box and the DRC will *not* complain
unless the via or trace clearance from the actual text is violated. I
do this often because my designs are very small and I typically need
every last bit of area I can get so using the bounding box would be
detrimental in my use case. Of course I could always ignore the
DRC but
I would rather the DRC give the proper checks I need.
>
> Currently, the drc test calculation is not optimized, so it needs
> refinements
> (mainly avoid to test the full text shape, when tracks or pads are
> outside the text bounding box)
>
> However the calculation time is low ( < 1 second), even with
complex and
> large boards.
>
_______________________________________________
Mailing list: https://launchpad.net/~kicad-developers
<https://launchpad.net/%7Ekicad-developers>
Post to : kicad-developers@xxxxxxxxxxxxxxxxxxx
<mailto:kicad-developers@xxxxxxxxxxxxxxxxxxx>
Unsubscribe : https://launchpad.net/~kicad-developers
<https://launchpad.net/%7Ekicad-developers>
More help : https://help.launchpad.net/ListHelp
_______________________________________________
Mailing list:https://launchpad.net/~kicad-developers
Post to :kicad-developers@xxxxxxxxxxxxxxxxxxx
Unsubscribe :https://launchpad.net/~kicad-developers
More help :https://help.launchpad.net/ListHelp
