kicad-developers team mailing list archive

[Cirilo Bernardo <cirilo.bernardo@xxxxxxxxx>]

The attached patch fixes a minor bug in the IDF export and includes trivial
code cleanup of the IDF and VRML export code. Under certain conditions the
IDF exporter spams the console with messages about unplaced components;
such components are now correctly assigned a placement value.

=== modified file 'pcbnew/exporters/export_idf.cpp'
--- pcbnew/exporters/export_idf.cpp	2014-06-24 16:17:18 +0000
+++ pcbnew/exporters/export_idf.cpp	2014-08-14 04:38:04 +0000
@@ -443,6 +443,9 @@
                         comp->SetPosition( aModule->GetPosition().x * scale + dx,
                                            -aModule->GetPosition().y * scale + dy,
                                            rotz, IDF3::LYR_BOTTOM );
+
+                comp->SetPlacement( IDF3::PS_ECAD );
+
             }
             else
             {

=== modified file 'utils/idftools/idf_parser.cpp'
--- utils/idftools/idf_parser.cpp	2014-08-03 07:48:41 +0000
+++ utils/idftools/idf_parser.cpp	2014-08-14 04:29:44 +0000
@@ -728,7 +728,8 @@
 
     if( aPlacement == PS_INVALID )
     {
-        ERROR_IDF << "placement invalid; defaulting to PLACED\n";
+        ERROR_IDF << "placement invalid (" << aRefDes << ":";
+        std::cerr << aPlacement << "); defaulting to PLACED\n";
         aPlacement = PS_PLACED;
     }
 

=== modified file 'utils/idftools/vrml_layer.cpp'
--- utils/idftools/vrml_layer.cpp	2014-08-12 16:03:50 +0000
+++ utils/idftools/vrml_layer.cpp	2014-08-12 21:10:51 +0000
@@ -30,7 +30,7 @@
 //    a closed loop as assumed for all other outlines.
 // 3. a scheme is needed to tell a castellated edge from a plain board edge
 
-#include <iostream>
+
 #include <sstream>
 #include <string>
 #include <iomanip>