kicad-developers team mailing list archive

[Andrew Zonenberg <azonenberg@xxxxxxxxxxxxxxx>]

I fixed the bug on my board the same way.

As of last time I checked, there is an automatic zone-fill before DRC
anyway. I've gotten in the habit of running DRC before taping out a
design since that both reruns zone fills and confirms that the fills are
good.

On Mon, 2014-11-17 at 18:47 +0000, Ian Woloschin wrote:
> That was my original thought, but I wasn't sure if that was too heavy
> handed since it could break existing designs?  Though of course,
> they'd be bad designs if they relied on this as a "feature".  If the
> choice is to force a zone re-fill I'd request that it does a zone
> re-fill before DRC as well.
> 
> 
> Should this be filed as a bug?  I'm happy to do so, but I thought this
> could benefit from some discussion first.
> 
> 
> The good news, I just found my 3/64 bits from the last time I did
> this, and drilling out the via through the inner layers does indeed
> disconnect my power and ground nets, so this was definitely my
> problem.  Easy enough to fix, especially since this was only 5
> prototype boards, but I'd have been real mad at myself if this was a
> large run!
> 
> 
> -Ian
> 
> On Mon Nov 17 2014 at 1:40:44 PM Andrew Zonenberg
> <azonenberg@xxxxxxxxxxxxxxx> wrote:
>         That bit me once too. Perhaps the best option is to force an
>         automatic
>         zone re-fill before exporting gerbers?
>         
>         On Mon, 2014-11-17 at 18:22 +0000, Ian Woloschin wrote:
>         > Hi folks,
>         >
>         >
>         > I had a question regarding a "sort-of-but-not-really" bug
>         that's
>         > bitten me a couple of times now.  Most of my boards now are
>         4 layers,
>         > with the two inner layers being Power/Ground zones.  This
>         generally
>         > works really well, but on at least two fairly complex
>         boards, I've had
>         > the misfortune of not remembering to quadruple check that no
>         zones are
>         > colliding with vias.  I believe this is usually caused by
>         forgetting
>         > to redraw zones after moving a via, which is entirely my own
>         fault,
>         > but I just did a quick check and I don't see any indication
>         of
>         > potentially colliding zones, and my DRC passes without any
>         issue :(.
>         > Can the DRC detect colliding Nets?  Is this something that
>         could be
>         > exposed via Python?
>         >
>         >
>         > Unfortunately I cannot share any of these boards, but it's
>         pretty easy
>         > to replicate this (4 layer board, punch a via through, fill
>         Inner
>         > layers with zones, move via, run DRC).
>         >
>         >
>         > In any case, I wanted to ask about this before filing a bug
>         report or
>         > feature request, because while it's not technically
>         incorrect
>         > behavior, it's behavior that is not intuitive based off of
>         all the
>         > other awesome things KiCad does for the board designer.
>         >
>         >
>         > -Ian
>         > _______________________________________________
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>         
>         --
>         Andrew Zonenberg
>         PhD student, security group
>         Computer Science Department
>         Rensselaer Polytechnic Institute
>         http://colossus.cs.rpi.edu/~azonenberg/
>         _______________________________________________
>         Mailing list: https://launchpad.net/~kicad-developers
>         Post to     : kicad-developers@xxxxxxxxxxxxxxxxxxx
>         Unsubscribe : https://launchpad.net/~kicad-developers
>         More help   : https://help.launchpad.net/ListHelp

-- 
Andrew Zonenberg
PhD student, security group
Computer Science Department
Rensselaer Polytechnic Institute
http://colossus.cs.rpi.edu/~azonenberg/

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