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Message #17580
Re: [patch] demos/ schematic tidying
Le 22/03/2015 23:21, Chris Pavlina a écrit :
> Noticed recently that the schematics in the demos/ directory are... a
> little grim. We could use some tidier schematics for demos, it shows off
> the software better.
>
> Here's a patch that cleans up these things:
>
> - More consistent alignment of similar parts in a schematic - don't
> scatter them so much.
>
> - More consistent placement of PWR_FLAGs - should be near power entry.
>
> - No f-off tiny fonts in critical places where people really need to be
> able to read them. Refdes and values should be 50mil minimum, power
> labels should be 40mil minimum
>
> - Bit of alignment in the placement of refdes/values.
>
> - Consistently orient circuits according to positive->negative
> vertically and input->output horizontally
>
> - Many of them have text in two languages. I replaced that with English
>
> - Remove overlaps, especially between components and the recently
> upsized title block, and for some reason, reference designators of
> transistors.
>
> - Avoid four-way junctions
>
> - Align more consistently to a 100mil grid, not 50mil.
>
> - Make connections with wires instead of just dropping pins on pins, as
> this makes it easier to drag parts.
>
> - Added missing junction dots, removed a few extra ones.
>
> Use it if you like.
>
> Chris
I committed you patch, but due to a mistake, under my name.
I am very sorry.
Thanks.
--
Jean-Pierre CHARRAS
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