kicad-developers team mailing list archive

[Andy Peters <devel@xxxxxxxxx>]

I know, feature freeze! But I just want to put this out there before I forget. It was mentioned on the Kicad.info forum, and I just happened to add a hierarchical thing to a current design, so it stood out.

Consider a common use of hierarchical schematics. You have some lower-level thing which you need to replicate. You create a hierarchical sheet, draw the thing, and you give it say four ports, two inputs called In1 and In2, and two outputs called Out1 and Out2.

In the higher-up sheet, you have two instances of Thing. This instantiating sheet has four nets, Foo[4:1] and Bar[4:1]. You wire Foo1 and Foo2 to Thing 1’s inputs In1 and In2, and you wire Foo3 and Foo4 to Thing 2’s inputs In1 and In2. You do the same with Bar and the outputs.

Create the netlist for pcbnew. You’ll notice that nets that connect the top sheet to Thing1 and Thing2 get names like /Topsheet/Thing1/In1, /Topsheet/Thing2/In1 and /Topsheet/Thing2/Out2 and so forth. When you look at the footprint pads for those nets (and when you draw the traces), you see only the In1 and In2 netnames. So at a casual glance, you might think that the two nets In1 are the same and that the signals to the lower level things are tied together. That’s not the case; the netlist is correct and your design is fine.

So the request: can’t the names of the nets passed down through hierarchical ports be that of the top-level (instantiating) entity, and not that of the low level instance?

-a