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Re: more than one net name on a net

 

> On Sep 4, 2015, at 12:08 PM, Adam Wolf <adamwolf@xxxxxxxxxxxxxxxxxxxx> wrote:
> 
>> On Fri, Sep 4, 2015 at 2:06 PM, Andy Peters <devel@xxxxxxxxx> wrote:
>> Someone over on the eevblog pointed this out, so I tested it and verified that it’s indeed the case.
>> 
>> Eeschema’s ERC is perfectly happy to accept more than one net label on a net. As a simple test, I took an existing schematic where one net connected two pins. The net had a label. I added another local net label to that net and ran the ERC, and it didn’t complain at all.
>> 
>> I generated a pcbnew netlist and noticed how the netlister chose which name to use: alphabetical. So if I put two net labels “foo” and “bar” on the net, the netlister chose “bar” for that net’s name.
>> 
>> Now, I can see why it is necessary for hierarchical schematics to allow for net-name overrides (which are not actually overrides, the net name is built with a hierarchical name /top//lower/netname). But at the very least having two labels on a net should throw a warning, if not an outright ERC fail.
>> 
>> This was reported back in November 2011 with https://bugs.launchpad.net/kicad/+bug/911002 and kinda dropped on the floor.
> 
> This was recently discussed here--not sure what the resolution was: https://lists.launchpad.net/kicad-developers/msg19448.html

Apparently dropped on the floor.

-a

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