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Message #22919
Re: Slow performance in pcbnew (PNS/GAL only) on high-fanout nets
Le 02/02/2016 10:31, Tomasz Wlostowski a écrit :
> On 02.02.2016 10:29, Maciej Sumiński wrote:
>> Pads on the same net overlapping are *not* a DRC error.
>>> (Only overlapping holes could be a DRC error, although I am not
>>> sure)
>
> Hi Jean-Pierre,
>
> I would refine that:
> - overlapping pads within the same component are not an error
> - overlapping pads between different components is an error
>
> Cheers,
> Tom
>
Yes I agree.
However, testing overlapping pads could be made only after
moving/placing a footprint (or changing a clearance value).
Checking the courtyard layers (feature to do ...) could be a good
complement.
--
Jean-Pierre CHARRAS
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