kicad-developers team mailing list archive

["Thor-Arne" <lp@xxxxxxxxxxxxx>]

We’re not talking about forbidding hiding pins, as far as we’ve reached in this discussion we’re curently on giving a warning when setting a warning when a pin is set to hidden.

And we are talking about the DRC giving to warn about multiple net names on one net.

Nothing of  this should make anything worse, it will make it easier to spot errors caused by having multiple names on the same net.

Vias loosing their net is a comletly different matter.

From: Lachlan Audas 
Sent: Sunday, February 07, 2016 12:12 AM
To: Thor-Arne 
Subject: Re: [Kicad-developers] Discussion: Hidden Pins, Net labels

Forbidding hiding pin's will make importing design's from Other PCB package's a nightmare.

I'ts  already really hard, getting KiCad to import to Eagle files.

With  KiCad losing net-name's on wire's in Sch.

and unconnected track's and via's losing there net's in PCB with out any warning !


Add to that all the bug's in Eagle, it's a nightmare.


Don't make it even worse than it is already is !


Lachlan



On Sat, Feb 6, 2016 at 10:12 AM, Thor-Arne <lp@xxxxxxxxxxxxx> wrote:

  Then how is pcbnew supposed to know what's going to be connected?
  I have not been using hierarchies much, is the nets separated?

  -----Original Message----- From: jp charras
  Sent: Saturday, February 06, 2016 6:27 PM
  To: kicad-developers@xxxxxxxxxxxxxxxxxxx
  Subject: Re: [Kicad-developers] Discussion: Hidden Pins, Net labels


  Le 06/02/2016 18:12, Thor-Arne a écrit :

    I think the multiple netnames on the same net should be included in the
    roadmap v5 DRC check.
    This should as a minimum throw a warning as this might break the
    finished pcb.


  Multiple netnames on the same net are a frequent case when using
  hierarchies and especially complex hierarchies.


  -- 
  Jean-Pierre CHARRAS

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