kicad-developers team mailing list archive

[André S. <list.dev.kicad@xxxxxxxxxxxx>]

As I see it this is what it boils down to. 

Though I'm not sure if the current documentation about hidden pins reflects the actual (intended) behavior of hidden pins and (power) net connections and naming conventions. Would be great if someone could review this. 

  André 

On February 9, 2016 2:48:14 PM GMT+01:00, Wayne Stambaugh <stambaughw@xxxxxxxxx> wrote:
>Now that we've discussed this, we need to put together a task list that
>can be added to the road map so they don't get lost in the noise.  I
>propose adding an ERC improvement section to the Eeschema section of
>the
>version 5 road map.  As of right now, I have one definable task and
>that
>is to test for different label names on the same net and warn the user
>when that occurs.  Are there any other tasks that need to be added to
>this list from this discussion?
>
>On 2/7/2016 4:39 PM, Thor-Arne wrote:
>> Ok, that's about what I figured.
>> 
>> I still think a warning would be the proper response to multiple
>names
>> on a single net.
>> The DRC just needs to check that the nets only is assigned one net
>name
>> for each sheet,
>> or use the same method as the netlister to check the entire schematic
>> project.
>> 
>> I can se no reason to allow more than one name for each net as the
>> netlister will just select one and use that, which in the best case
>is
>> confusing for the user.
>> In worst case scenario you could end up with two power nets
>connected,
>> say 5V and 3.3V, which would be a major failure of the DRC.
>> 
>> -----Original Message----- From: Andy Peters
>> Sent: Sunday, February 07, 2016 10:20 PM
>> To: KiCad Developers
>> Subject: Re: [Kicad-developers] Discussion: Hidden Pins, Net labels
>> 
>> 
>>> On Feb 6, 2016, at 11:12 AM, Thor-Arne <lp@xxxxxxxxxxxxx> wrote:
>>>
>>> Then how is pcbnew supposed to know what's going to be connected?
>>> I have not been using hierarchies much, is the nets separated?
>> 
>> With hierarchical designs, the netlister builds net names into
>something
>> that looks like a Unix path.
>> 
>> Say you have a lower-level sheet called Foo.sch, and this sheet has a
>> net called Bar. Foo.sch is instantiated in a top-level schematic.
>Rename
>> its instance name of u_foo because the default is a jumbled
>unique-value
>> string.
>> 
>> The netlister will call that net /u_foo/Bar
>> 
>> If you have two instances of Foo.sch called u_foo_1 and u_foo_2, that
>> net Bar will NOT be the same (unless you make it global), and the
>> netlister creates two nets called /u_foo_1/bar and /u_foo_2/bar This
>is
>> how you can have multiple “channels” of replicated instances of
>> lower-level sheets. The annotator will assign unique reference
>> designators to the components on the sheets, so an op-amp in u_foo_1
>> might be called U12 and that same symbol in u_foo_2 might be called
>U18.
>> 
>> An even more interesting situation. Say you have a schematic
>> microcontroller.sch which is instantiated in the top level as
>u_micro,
>> and this sheet has two outputs foo and bar. Say you have another
>> schematic output.sch which is also instantiated in the top level as
>> u_output, and this sheet takes foo and bar in as inputs. The
>netlister
>> will give you nets called /u_micro/foo and /u_micro/bar
>> 
>> -a
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