kicad-developers team mailing list archive

[Chris Pavlina <pavlina.chris@xxxxxxxxx>]

Ah, no - I got a bit off scope there, I'm talking about the whole
project.  Generating the netlist in eeschema is very slow, which means
sch->pcb sync is slow. Not necessarily a task for you specifically, I'm
just kind of enumerating the bits where kicad's been annoying me on this
project.
:)

On Fri, Aug 12, 2016 at 06:16:05PM +0200, Tomasz Wlostowski wrote:
> On 12.08.2016 15:22, Chris Pavlina wrote:
> > - Netlist generation. I had a go at rewriting the algorithm for this
> >   (it's O(n^3) and doesn't need to be...) but didn't get very far with
> >   limited time.
> Do you mean ratsnest?
> 
> Cheers,
> T.