kicad-developers team mailing list archive

[jp charras <jp.charras@xxxxxxxxxx>]

Le 12/08/2016 à 18:26, Chris Pavlina a écrit :
> Ah, no - I got a bit off scope there, I'm talking about the whole
> project.  Generating the netlist in eeschema is very slow, which means
> sch->pcb sync is slow. Not necessarily a task for you specifically, I'm
> just kind of enumerating the bits where kicad's been annoying me on this
> project.
> :)

Are you sure ?
I downloaded and tested your motherboard project.
Building the netlist is very fast (less than 1 second on my computer).
sch->pcb sync takes roughly 1s.

only the DRC is time consuming because you have 41000 track segments.

> 
> On Fri, Aug 12, 2016 at 06:16:05PM +0200, Tomasz Wlostowski wrote:
>> On 12.08.2016 15:22, Chris Pavlina wrote:
>>> - Netlist generation. I had a go at rewriting the algorithm for this
>>>   (it's O(n^3) and doesn't need to be...) but didn't get very far with
>>>   limited time.
>> Do you mean ratsnest?
>>
>> Cheers,
>> T.
> 
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-- 
Jean-Pierre CHARRAS