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Re: Via Stitching

 

24/09/16, 18:55, Collin Anderson kirjoitti:
> I do lots of DC/DC stuff with power dissipation one of my primary concerns - so I stitch and I stitch A LOT.

Some of the following may be redundant so feel free to skip... ;)

Regarding components that need thermal vias it's best to define them in
the library model. This way there are no hacks needed like multiple
segment GND-pads, etc. The copper pad, the thermal vias and the paste
prints neatly separated and defined.

That way it's easy to segment paste so that it doesn't go on/in the vias
and the paste openings can have rounded corners etc. optimizations. No
need for expensive plugged vias or problems with solder oozing to the
other side. This has been production tested on QFN-52 and TO-263.

The via stitching should be a part of zone filling definitions, so that
edges could be automatically traced and the center filled with a pattern
(with different parameters). Just a via fill mode should be provided too
to make islands of vias within a zone.

-Vesa



References