kicad-developers team mailing list archive

[José Ignacio <jose.cyborg@xxxxxxxxx>]

While changing the format it would also be great if a separate clearance
could be specified between the zone and board edges vs trace clearances, at
least leave the capability in the format if it can't be implemented yet.
I've found that the required copper pullback in some cases is much higher
than what would be desirable for regular zone-trace clearances, which
required me to get creative with the zone outlines.

Thanks,
Jose

On Sun, Apr 30, 2017 at 5:32 PM, Tomasz Wlostowski <
tomasz.wlostowski@xxxxxxx> wrote:

> On 30.04.2017 21:02, Lachlan Audas wrote:
> > Here's the link,
> > http://www.cosmosc.com/example/A10-A20-OLINUXINO-MICRO-4GB_Rev_D.brd
> > it's in eagle format, so import  under pcbnew.
> > I should of added that viewing the (E)properties and make no changes
> > (but hitting the OK instead of the Cancel button)  regenerates the flood
> > fill.
> > while not wrong,   it may be worth adding a change bit,   to the
> > properties requester,   and only regenerates if something has changed.
> > But I suppose that's nit picking ;)
> >
>
> Hi,
>
> Lachlan sent me a complex board in Eagle that has several copper zones,
> each with different clearances, which filled incorrectly or didn't fill
> at all. There were some trivial issues (e.g. inverted filling priority),
> but there is one that needs discussion:
>
> In pcbnew, each zone must have manually assignned clearance (in the
> property window). In Eagle or Altium, if there's no clearance specified,
> the program takes the clearance set in the Design Rules for the net the
> zone belongs to.
>
> I propose to add a similar feature to Kicad, that is:
> - add a checkbox "use custom clearance" in the zone properties window
> - if not checked, take the netclass clearance.
>
> This unfortunately requires a small file format change. Would you agree
> with that?
>
> Also, many thanks to Lachlan for spotting this problem!
>
> Cheers,
> Tom
>
>
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