kicad-developers team mailing list archive

[Wayne Stambaugh <stambaughw@xxxxxxxxx>]

On 7/24/2017 6:12 PM, hauptmech wrote:
> 
> Yeah, it's weird since all I'm doing when collecting perf data is
> zooming and panning the pcb, (with eeschema open).  A root page and 11
> sub pages at the next level. Roughly 800 components and 2000 wires.
> 
> Probably something somewhere is instantiating a new SCH_SHEET_LIST
> (which then has to chew through each and every schematic item to find
> the sheets) on every event?

This is even more disturbing.  When did we start building the sheet list
in pcbnew and more importantly why?

> 
> 
> 
> On 25/07/17 01:59, Wayne Stambaugh wrote:
>> On 7/23/2017 7:36 PM, hauptmech wrote:
>>> I'm getting a distracting amount of lag when panning and zooming with
>>> GAL. Perf reports TOOL_MANAGER::dispatchInternal and, when eeschema is
>>> open, SCH_SHEET_LIST::BuildSheetList, as the main time sinks.
>> Given that all BuildSheetList does is create a list of unique sheets in
>> a schematic, I find it difficult to believe that you would have that
>> many sheets (hierarchical or otherwise) that would cause a performance
>> hit.  How many sheets does your design have and how deeply are they
>> nested?
>>
>>> Anyone have any hints for me improve this?
>>>
>>> In general I'm getting the impression that the design I'm working on is
>>> a bit more complex than the developers normally test on. I'll see if my
>>> client will allow a sanitized version of this board to go into /demos.
>>>
>>> -hauptmech
>>>
>>>
>>>
>>>
>>>
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> 
> 
> 
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