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Message #30389
Re: Additional Patch for via properties dialog (2)
I have created KiPadCheck as a post-layout DRC addition to KiCad. It has some checks related to pads, vias, drill, silkscreen, paste, and mask that address some shortcomings in KiCad DRC. I have also researched Eagle's DRC and they allow a fairly wide range of specifications for layers, vias and pads.
For example, the layers definition page, https://i.stack.imgur.com/X0zvH.png,has the ability to specify thicknesses for prepreg and core as well as fairly detailed informationon via placement between specified layers. It might be useful as an example of what can be done.
The clearance screen (figure 1.1 at http://sensi.org/~svo/gerberhowto/index.en.html)and the REST-RING (the second graphic here: https://forum.kicad.info/t/drc-drill-to-track-clearance/7311/9) tab show the various available DRC rules the Eagle uses.
I'm trying to get KiPadCheck and design rule save/load to work with DRU files. I'll lbe able to getback to that when LayerViewSet is closer to complete.
Does any of this help the conversation here about via properties?
On Tuesday, August 22, 2017 2:36 PM, Wayne Stambaugh <stambaughw@xxxxxxxxx> wrote:
On 8/22/2017 8:05 AM, Bastian Neumannn wrote:
> Hi
>
>> Ultimately is it useful to design a board, if you cannot make it?
>
> Right now I can fabricate boards, I can not design. That is also not a
> good solution.
>
> via constraints are tricky bussiness as they are very specific to the
> manufacturer.
I'm not opposed to this change. However, there are two schools of
thought when it comes to board layout: strict layout constraints and no
layout constraints. I tend to lean towards the latter but I've been
doing this for 30 years so I am painfully aware of the pitfalls of no
layout constraints and have a pretty good idea of what not to do.
Should we choose to loosen the layout constraints for blind/buried vias,
then we should be prepared for a serious tongue lashing the first time
someone violates their board vendor's manufacturing limitations and ends
up with a bunch of useless and likely expensive boards. Maybe at some
point in the future we will have a complete constraint system that can
cover all possibilities but until then we have to walk that fine line
between power users and beginners.
>
>> PS:
>> The current "tracks and vias editor" dialog is (for me) a not finished work:
>> It does not make any DRC test after editing, and this is *really annoying*.
>
> This is what I am working on at the moment. To have a propper mask where
> one can input constraints for vias.
>
> At the moment you can only define some layers. There is much more work
> to do. Like staggered/stacked µvias
>
> Inline-Bild 2
>
> Based on this dialog I plan on having more layer masks to only show
> layers described here.
>
> Cheers
>
> 2017-08-22 13:00 GMT+02:00 jp charras <jp.charras@xxxxxxxxxx
> <mailto:jp.charras@xxxxxxxxxx>>:
>
> Le 22/08/2017 à 12:10, Simon Küppers a écrit :
> > I second this. Working in a Research Institute I can assure you, that very often there are circuit
> > boards with "interesting" stackups and via configurations... These boards are not produced by
> > quick-turn factories like eurocircuits but companies such as ILFA or Optiprint.
> >
> > It would be unwise to cut out those users from KiCad.
>
> I dont't remember I said we should restrict vias to eurocircuits
> constraints.
>
> Moreover "very often there are circuit boards with "interesting"
> stackups and via configurations"
> lead me to think there are constraints, unless I missed something.
> (if there are "via configurations", there are constraints)
>
> I don't think eurocircuits is at quick-turn factory (although I have
> myself any experience about
> blind/buried vias) but I think blind/buried vias can have
> constraints, because I saw constraints in
> board houses.
>
> Ultimately is it useful to design a board, if you cannot make it?
>
> In fact, Pcbnew is really lacking a board stackup editor, to define
> not only the stackup layers, but
> some other parameters (via parameters, copper thickness, dielectric
> thickness and type, and a few
> other parameters).
>
> This board stackup definition is needed not only for vias, but also
> for impedance controlled boards.
>
> PS:
> The current "tracks and vias editor" dialog is (for me) a not
> finished work:
> It does not make any DRC test after editing, and this is *really
> annoying*.
>
>
> >
> >
> > Am 2017-08-22 09:57, schrieb hauptmech:
> >> On 22/08/17 18:25, jp charras wrote:
> >>> Le 22/08/2017 à 05:55, hauptmech a écrit :
> >>>> Manufacturing techniques vary between manufacturers and
> continuously evolve. Why would kicad limit
> >>>> itself to what eurocircuits can do? They have optimized their
> process for quick turn prototyping
> >>>> and
> >>>> while they document their process nicely, they are probably not
> a good reference for what can be
> >>>> done.
> >>>>
> >>>> On 21/08/17 05:44, jp charras wrote:
> >>>>> Before working on blind and buried vias dialog, please have a
> look at:
> >>>>> https://www.eurocircuits.com/blog/Blind-and-buried-vias
> <https://www.eurocircuits.com/blog/Blind-and-buried-vias>
> >>> Currently there is no control in Kicad.
> >>>
> >>> Sure, but it looks like there are some constraints on
> blind/buried vias (microvias are blind/buried
> >>> vias) depending on board houses.
> >>>
> >>> So it could be worth to be able to control these constraints
> inside Kicad (at least to have a
> >>> minimal control).
> >>>
> >>> We currently have a DRC which detects too small clearances and
> track widths:
> >>> this is most of time due to manufacturing constraints which
> continuously evolve.
> >>>
> >> I don't think I have enough understanding of the proposal to have an
> >> opinion. I just want to caution against creating unnecessary
> >> limitations in kicad. It really depends on the board house. I used to
> >> work for one and there were quite a few atypical techniques used for
> >> customer specific projects (many kept confidential to that customer).
> >>
> >>
> >>
> >>
> >>
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>
> --
> Jean-Pierre CHARRAS
>
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