kicad-developers team mailing list archive

[Eeli Kaikkonen <eeli.kaikkonen@xxxxxxxxx>]

I'm not a KiCad developer, but may have something useful to say before the
developers take part in the discussion (they may be busy with FOSDEM right
now). First, have you looked at the bug database? Some of your wishes are
already well known and even planned for the future. See
https://bugs.launchpad.net/kicad/+bugs?orderby=-heat&start=0 (ordered by
"heat" which roughly can be taken as user interest level).

At least 2a and 2e are high in the wish list. 2d is possibly touched by two
items, "PcbNew group components
<https://bugs.launchpad.net/kicad/+bug/1494079>" and "Support for repeating
subcircuits/channels/rooms <https://bugs.launchpad.net/kicad/+bug/1521062>".
2g and also 2j might be part of the constraint system planned for 6.0
(mentioned earlier today in the FOSDEM 2019 presentation by Wayne
Stambaugh, https://fosdem.org/2019/schedule/event/kicad/), it has been
discussed here.

I really hope you will find a way to sponsor some of these!

Eeli Kaikkonen

pe 1. helmik. 2019 klo 19.56 Schaarschmidt Wolf (wolf@xxxxxxxxxxx)
kirjoitti:

> Dear KiCad developers,
>
> our company Dorabot is an enthusiastic KiCad user,
> so we would like to *sponsor *some improvements:
>
> *1. Schematic design part*
> a. provide off-page connection for a parallel bus.
> b. provide customized power ports that can be edited by netlabel in case
> there are several power rails.
> c. provide a convenient way to duplicate circuitry partially from another
> project.
> d. provide a convenient way to combine two different schematic-libs.
> e. provide a way to import schematic designs from other popular EDA tools,
> such as Altium Designer or Orcad.
>
> *2. PCB layout part*
> a. provide teardrop connection methods, including mass and individual way.
> b. provide a method to mass align REF numbers.
> c. provide a method to mass edit the size of REF numbers.
> d. provide a method to move multiple components in *PCB* when selected in
> the schematic.
> e. provide a method to add arc traces.
> f.  provide a method to add polygons with arc corners.
> g. have a specified rule to constrain the clearance between the edge and
> polygons or traces locally (not only globally).
> h. provide a way to import PCB designs from other popular EDA tools, such
> as Altium Designer or Allegro.
> i.  provide a convenient way to fanout BGA footprints with certain VIA
> size and Trace width.
> j.  provide region constraint for small pitch size BGA footprint.
>
> Please let us know whether you see an opportunity for us to *sponsor* (i.e.
> financially support)
> some or all of these improvements. We are looking forward to hearing from
> you!
>
> Best regards,
>
> *Wolf Schaarschmidt*｜Robot Engineer
>
> wolf@xxxxxxxxxxx <Meiyu.bao@xxxxxxxxxxx%EF%BD%9C(+86)>
>
>
> No. 2 Zuopaotai Rd, H6-2, Nanshan District｜Shenzhen, Guangdong 518000,
> China
>
> 0755-21650236｜ <info@xxxxxxxxxxx%EF%BD%9Cwww.dorabot.com>info@xxxxxxxxxxx｜
> www.dorabot.com
>
>
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