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Re: Kicad's way of drawing filled zones
Am 2019-05-10 12:33, schrieb Tomasz Wlostowski:
I've been recently playing with Victor's huge 32-layer PCB design and
trying to improve the performance of pcbnew for larger designs. This
board causes even pretty decent PCs to crash/render glitches due to
pcbnew's enormous VBO (Vertex Buffer) memory consumption.
It turns out it's caused by the way KiCad renders filled zones:
- the inside of a zone is drawn/plotted as a filled polygon with
boundary. This one not a problem - we already triangulate the polygons
and I recently developed a patch for the OpenGL GAL that allows reusing
vertices of triangulated polys in the VBO/Index buffer to further
- the thick outline is drawn with rounded segments with the width =
minimum width of the polygon. Since we don't have arcs in polygons,
of round features (e.g. vias) surrounded by a zone gets a ton of tiny
segments in the polygon outline. Each rounded segment in OpenGL is
composed of 2 triangles, hence 6 vertices (that can't be reused...).
Victor's board it means 1 GB (sic!) of the VBO goes for outlines of the
polygons alone. Disabling the outline drawing makes the renderer work
What about moving the knock-out code to the relative-error calculation
first? Vias probably don't need 32 segments around the edge. Look at
buildZoneFeatureHoleList(). We currently use 32 as the minimum value
for segments per circle, so each via with a cutout has 32 segments, each
of which have 32*3 points for the rounded edges. So that's 3k worth of
points per via. If we moved to the relative error for the vias, most
would be at ~14 segments (for a 6-mil via with 6 mil clearance) or only
Most of the code for the relative calculation is in place already. We
need to finish updating routines line
TransformShapeWithClearanceToPolygon() and Inflate() to remove their
dependence on segment count.
This might avoid the need for massive overhaul of the graphics engine.