kicad-developers team mailing list archive

[Jeff Young <jeff@xxxxxxxxx>]

I’ve pushed new bits which fix this corner case, and some performance enhancements to make up for the extra processing required.

> On 23 Jun 2019, at 10:01, jp charras <jp.charras@xxxxxxxxxx> wrote:
> 
> Le 22/06/2019 à 20:23, Jeff Young a écrit :
>> Hi JP,
>> 
>> Can you point me to some of the clearance violation issues?
>> 
>> I’m aware of the one where a track that goes within the thermal clearance radius can produce a DRC error, but I’d consider that what DRC is for.  But it sounds like there are others?
>> 
>> Thanks,
>> Jeff.
>> 
> 
> Hi Jeff,
> 
> I attached a board that exhibit a DRC error between a pad and a thermal
> stub.
> See U2, pads 6 and 7.
> The clearance is roughly 0.22 mm, but the GND min clearance is 0.28mm
> and the zone clearance is 0.5mm
> 
>> 
>>> On 22 Jun 2019, at 18:58, jp charras <jp.charras@xxxxxxxxxx> wrote:
>>> 
>>> Le 22/06/2019 à 18:37, Jeff Young a écrit :
>>>> New, higher-performance bits in, with some (perhaps all) of the bugs fixed.
>>>> 
>>>> Testing would be appreciated.
>>>> 
>>>> Cheers,
>>>> Jeff.
>>>> 
>>> 
>>> Hi Jeff,
>>> 
>>> Usually, when 2 bugs are fixed, one new bug is created.
>>> 
>>> Thermal stubs are missing for pads having a different size in X and Y
>>> direction.
>>> They are missing for the biggest direction.
>>> 
>>> Apart from that:
>>> * The calculation time is bigger than the current algo, but no longer
>>> blocking (for instance 2 sec instead of less than 1 sec in a bad case).
>>> * Much more annoying, the thermal stubs can create DRC issues:
>>> They do not always respect the zone clearance, and in some cases do not
>>> respect the netclass clearance.
>>> 
>>> They also create some shape artifacts.
>>> They are of course not the same as the current algo, but they exist.
>>> 
>>> -- 
>>> Jean-Pierre CHARRAS
> 
> -- 
> Jean-Pierre CHARRAS
> <pic_programmer_test_zone.kicad_pcb>