maria-developers team mailing list archive

[Kristian Nielsen <knielsen@xxxxxxxxxxxxxxx>]

Hi Paul,

It seems a patch is needed for PBXT to build on 32-bit x86 in some cases:

Elena Stepanova <elenst@xxxxxxxxxxxxxxxx> writes:

> lock_xt.h: Assembler messages:
> lock_xt.h:70: Error: bad register name `%sil'

> After some re-installation and long digging, I found the ancient bug
> report http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10153 which gets
> re-filed regularly, the last time was a few months ago. They say it's
> a code problem, and suggest replacing the '=r' constraint with '=q'. I
> did so in all 4 lines that gcc complained about, and finally got it
> work.

It seems correct to me that the "q" constraint must be used rather than "r"
for the 8-bit case. Below patch should do it (we will apply this in MariaDB).

 - Kristian.

=== modified file 'storage/pbxt/src/lock_xt.h'
--- storage/pbxt/src/lock_xt.h	2010-05-06 12:57:15 +0000
+++ storage/pbxt/src/lock_xt.h	2011-12-12 11:34:54 +0000
@@ -67,9 +67,9 @@ inline void xt_atomic_inc1(volatile xtWo
 #elif defined(XT_ATOMIC_GNUC_X86)
 	xtWord1 val;
 
-	asm volatile ("movb %1,%0" : "=r" (val) : "m" (*mptr) : "memory");
+	asm volatile ("movb %1,%0" : "=q" (val) : "m" (*mptr) : "memory");
 	val++;
-	asm volatile ("xchgb %1,%0" : "=r" (val) : "m" (*mptr), "0" (val) : "memory");
+	asm volatile ("xchgb %1,%0" : "=q" (val) : "m" (*mptr), "0" (val) : "memory");
 #elif defined(XT_ATOMIC_SOLARIS_LIB)
 	atomic_inc_8(mptr);
 #else
@@ -91,9 +91,9 @@ inline xtWord1 xt_atomic_dec1(volatile x
 #elif defined(XT_ATOMIC_GNUC_X86)
 	xtWord1 val2;
 
-	asm volatile ("movb %1, %0" : "=r" (val) : "m" (*mptr) : "memory");
+	asm volatile ("movb %1, %0" : "=q" (val) : "m" (*mptr) : "memory");
 	val--;
-	asm volatile ("xchgb %1,%0" : "=r" (val2) : "m" (*mptr), "0" (val) : "memory");
+	asm volatile ("xchgb %1,%0" : "=q" (val2) : "m" (*mptr), "0" (val) : "memory");
 	/* Should work, but compiler makes a mistake?
 	 * asm volatile ("xchgb %1, %0" : : "r" (val), "m" (*mptr) : "memory");
 	 */