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Message #00033
[PATCH] cpudepend.h: move from <mach/> to <asm/>
From: Du Huanpeng <u74147@xxxxxxxxx>
Signed-off-by: Du Huanpeng <u74147@xxxxxxxxx>
---
.../monitor/hwdepend/arm/include/asm/cpudepend.h | 92 +++++++++++++++++++++
.../arm/mach-acd2/include/mach/cpudepend.h | 96 ----------------------
.../arm/mach-asm9/include/mach/cpudepend.h | 96 ----------------------
.../monitor/hwdepend/arm/mach-mx28/icoll.c | 2 +-
.../arm/mach-mx28/include/mach/cpudepend.h | 92 ---------------------
.../arm/mach-sam9/include/mach/cpudepend.h | 96 ----------------------
tkernel_source/monitor/include/tmonitor.h | 2 +-
7 files changed, 94 insertions(+), 382 deletions(-)
create mode 100644 tkernel_source/monitor/hwdepend/arm/include/asm/cpudepend.h
delete mode 100644 tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h
delete mode 100644 tkernel_source/monitor/hwdepend/arm/mach-asm9/include/mach/cpudepend.h
delete mode 100644 tkernel_source/monitor/hwdepend/arm/mach-mx28/include/mach/cpudepend.h
delete mode 100644 tkernel_source/monitor/hwdepend/arm/mach-sam9/include/mach/cpudepend.h
diff --git a/tkernel_source/monitor/hwdepend/arm/include/asm/cpudepend.h b/tkernel_source/monitor/hwdepend/arm/include/asm/cpudepend.h
new file mode 100644
index 0000000..93676bc
--- /dev/null
+++ b/tkernel_source/monitor/hwdepend/arm/include/asm/cpudepend.h
@@ -0,0 +1,92 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ * rewrite io access operation, because the origianl inline routines
+ * does not realy inline when compile with gcc.
+ *
+ * Copyright 2016 Du Huanpeng <u74147@xxxxxxxxx>
+ */
+
+/*
+ * cpudepend.h
+ *
+ * ARM-related definitions
+ */
+
+#ifndef __MONITOR_ARM_CPUDEPEND_H__
+#define __MONITOR_ARM_CPUDEPEND_H__
+
+#include <machine.h>
+#include <typedef.h>
+
+/*
+ * monitor stack area
+ * stack area is from &__stack_top to &__stack_bottom
+ * initial stack pointer = &__stack_bottom
+ */
+IMPORT UB __stack_top, __stack_bottom;
+
+/*
+ * first level page table
+ */
+IMPORT UW* const TopPageTable; /* location of page table */
+#define N_PageTableEntry 0x1000 /* number of entries */
+
+/*
+ * address conversion to non-cached and cached area
+ * in the case of ARM, all address have the same cache mode, and hence
+ * return as it is.
+ */
+#define NOCACHE_ADDR(p) (p)
+#define CACHE_ADDR(p) (p)
+
+/*
+ * I/O port access functions
+ */
+
+
+#define out_w(port, data) ((*(volatile unsigned long *)(port)) = (unsigned long)(data))
+#define out_h(port, data) ((*(volatile unsigned short *)(port)) = (unsigned short)(data))
+#define out_b(port, data) ((*(volatile unsigned char *)(port)) = (unsigned char)(data))
+
+#define in_w(port) (*(volatile unsigned long *)(port))
+#define in_h(port) (*(volatile unsigned short *)(port))
+#define in_b(port) (*(volatile unsigned char *)(port))
+
+/*
+ * value of control register (r1) of system control coprocessor cp15
+ */
+#if __TRON_ARM_ARCH == 6
+#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
+#define VALID_CACHEMMU (0x3307) /* B = 0 */
+#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
+#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
+#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
+#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
+#else
+#define MASK_CACHEMMU (0) /* V,I,R,S,C,A,M (B = 0) */
+#define VALID_CACHEMMU (0) /* B = 0 */
+#define DIS_CACHEMMU (0) /* I=0,R=0,S=0,C=0,A=0,M=0 */
+#define DIS_CACHEONLY (0) /* I=0,R=0,S=0,C=0,A=0,M=1 */
+#define ENB_CACHEMMU (0) /* I=1,R=0,S=0,C=1,A=1,M=1 */
+#define ENB_MMUONLY (0) /* I=0,R=0,S=0,C=0,A=1,M=1 */
+#endif
+
+/*
+ * references registers under monitor control
+ * references the value of registers at the time of monitor entry.
+ */
+IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
+IMPORT UW getCurPCX( void ); /* PC register (raw value) */
+IMPORT UW getCurCPSR( void ); /* CPSR register */
+
+#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h b/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h
deleted file mode 100644
index 4cbb714..0000000
--- a/tkernel_source/monitor/hwdepend/arm/mach-acd2/include/mach/cpudepend.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cpudepend.h
- *
- * ARM-related definitions
- */
-
-#ifndef __MONITOR_ARM_CPUDEPEND_H__
-#define __MONITOR_ARM_CPUDEPEND_H__
-
-#include <machine.h>
-
-/*
- * monitor stack area
- * stack area is from &__stack_top to &__stack_bottom
- * initial stack pointer = &__stack_bottom
- */
-IMPORT UB __stack_top, __stack_bottom;
-
-/*
- * first level page table
- */
-IMPORT UW* const TopPageTable; /* location of page table */
-#define N_PageTableEntry 0x1000 /* number of entries */
-
-/*
- * address conversion to non-cached and cached area
- * in the case of ARM, all address have the same cache mode, and hence
- * return as it is.
- */
-#define NOCACHE_ADDR(p) (p)
-#define CACHE_ADDR(p) (p)
-
-/*
- * I/O port access functions
- */
-Inline void out_w( INT port, UW data )
-{
- *(_UW*)port = data;
-}
-Inline void out_h( INT port, UH data )
-{
- *(_UH*)port = data;
-}
-Inline void out_b( INT port, UB data )
-{
- *(_UB*)port = data;
-}
-
-Inline UW in_w( INT port )
-{
- return *(_UW*)port;
-}
-Inline UH in_h( INT port )
-{
- return *(_UH*)port;
-}
-Inline UB in_b( INT port )
-{
- return *(_UB*)port;
-}
-
-/*
- * value of control register (r1) of system control coprocessor cp15
- */
-#if CPU_ARM1176
-#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
-#define VALID_CACHEMMU (0x3307) /* B = 0 */
-#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
-#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
-#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
-#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
-#endif
-
-/*
- * references registers under monitor control
- * references the value of registers at the time of monitor entry.
- */
-IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
-IMPORT UW getCurPCX( void ); /* PC register (raw value) */
-IMPORT UW getCurCPSR( void ); /* CPSR register */
-
-#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-asm9/include/mach/cpudepend.h b/tkernel_source/monitor/hwdepend/arm/mach-asm9/include/mach/cpudepend.h
deleted file mode 100644
index 4cbb714..0000000
--- a/tkernel_source/monitor/hwdepend/arm/mach-asm9/include/mach/cpudepend.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cpudepend.h
- *
- * ARM-related definitions
- */
-
-#ifndef __MONITOR_ARM_CPUDEPEND_H__
-#define __MONITOR_ARM_CPUDEPEND_H__
-
-#include <machine.h>
-
-/*
- * monitor stack area
- * stack area is from &__stack_top to &__stack_bottom
- * initial stack pointer = &__stack_bottom
- */
-IMPORT UB __stack_top, __stack_bottom;
-
-/*
- * first level page table
- */
-IMPORT UW* const TopPageTable; /* location of page table */
-#define N_PageTableEntry 0x1000 /* number of entries */
-
-/*
- * address conversion to non-cached and cached area
- * in the case of ARM, all address have the same cache mode, and hence
- * return as it is.
- */
-#define NOCACHE_ADDR(p) (p)
-#define CACHE_ADDR(p) (p)
-
-/*
- * I/O port access functions
- */
-Inline void out_w( INT port, UW data )
-{
- *(_UW*)port = data;
-}
-Inline void out_h( INT port, UH data )
-{
- *(_UH*)port = data;
-}
-Inline void out_b( INT port, UB data )
-{
- *(_UB*)port = data;
-}
-
-Inline UW in_w( INT port )
-{
- return *(_UW*)port;
-}
-Inline UH in_h( INT port )
-{
- return *(_UH*)port;
-}
-Inline UB in_b( INT port )
-{
- return *(_UB*)port;
-}
-
-/*
- * value of control register (r1) of system control coprocessor cp15
- */
-#if CPU_ARM1176
-#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
-#define VALID_CACHEMMU (0x3307) /* B = 0 */
-#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
-#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
-#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
-#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
-#endif
-
-/*
- * references registers under monitor control
- * references the value of registers at the time of monitor entry.
- */
-IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
-IMPORT UW getCurPCX( void ); /* PC register (raw value) */
-IMPORT UW getCurCPSR( void ); /* CPSR register */
-
-#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c b/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c
index 05eac07..38b4fd0 100644
--- a/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c
+++ b/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c
@@ -24,7 +24,7 @@
#include "regs-icoll.h"
#include <mach/mx28.h>
-#include <mach/cpudepend.h>
+#include <asm/cpudepend.h>
#include <tmonitor.h>
#include <typedef.h>
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-mx28/include/mach/cpudepend.h b/tkernel_source/monitor/hwdepend/arm/mach-mx28/include/mach/cpudepend.h
deleted file mode 100644
index 93676bc..0000000
--- a/tkernel_source/monitor/hwdepend/arm/mach-mx28/include/mach/cpudepend.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- * rewrite io access operation, because the origianl inline routines
- * does not realy inline when compile with gcc.
- *
- * Copyright 2016 Du Huanpeng <u74147@xxxxxxxxx>
- */
-
-/*
- * cpudepend.h
- *
- * ARM-related definitions
- */
-
-#ifndef __MONITOR_ARM_CPUDEPEND_H__
-#define __MONITOR_ARM_CPUDEPEND_H__
-
-#include <machine.h>
-#include <typedef.h>
-
-/*
- * monitor stack area
- * stack area is from &__stack_top to &__stack_bottom
- * initial stack pointer = &__stack_bottom
- */
-IMPORT UB __stack_top, __stack_bottom;
-
-/*
- * first level page table
- */
-IMPORT UW* const TopPageTable; /* location of page table */
-#define N_PageTableEntry 0x1000 /* number of entries */
-
-/*
- * address conversion to non-cached and cached area
- * in the case of ARM, all address have the same cache mode, and hence
- * return as it is.
- */
-#define NOCACHE_ADDR(p) (p)
-#define CACHE_ADDR(p) (p)
-
-/*
- * I/O port access functions
- */
-
-
-#define out_w(port, data) ((*(volatile unsigned long *)(port)) = (unsigned long)(data))
-#define out_h(port, data) ((*(volatile unsigned short *)(port)) = (unsigned short)(data))
-#define out_b(port, data) ((*(volatile unsigned char *)(port)) = (unsigned char)(data))
-
-#define in_w(port) (*(volatile unsigned long *)(port))
-#define in_h(port) (*(volatile unsigned short *)(port))
-#define in_b(port) (*(volatile unsigned char *)(port))
-
-/*
- * value of control register (r1) of system control coprocessor cp15
- */
-#if __TRON_ARM_ARCH == 6
-#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
-#define VALID_CACHEMMU (0x3307) /* B = 0 */
-#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
-#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
-#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
-#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
-#else
-#define MASK_CACHEMMU (0) /* V,I,R,S,C,A,M (B = 0) */
-#define VALID_CACHEMMU (0) /* B = 0 */
-#define DIS_CACHEMMU (0) /* I=0,R=0,S=0,C=0,A=0,M=0 */
-#define DIS_CACHEONLY (0) /* I=0,R=0,S=0,C=0,A=0,M=1 */
-#define ENB_CACHEMMU (0) /* I=1,R=0,S=0,C=1,A=1,M=1 */
-#define ENB_MMUONLY (0) /* I=0,R=0,S=0,C=0,A=1,M=1 */
-#endif
-
-/*
- * references registers under monitor control
- * references the value of registers at the time of monitor entry.
- */
-IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
-IMPORT UW getCurPCX( void ); /* PC register (raw value) */
-IMPORT UW getCurCPSR( void ); /* CPSR register */
-
-#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-sam9/include/mach/cpudepend.h b/tkernel_source/monitor/hwdepend/arm/mach-sam9/include/mach/cpudepend.h
deleted file mode 100644
index 4cb6193..0000000
--- a/tkernel_source/monitor/hwdepend/arm/mach-sam9/include/mach/cpudepend.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- *----------------------------------------------------------------------
- * T-Kernel 2.0 Software Package
- *
- * Copyright 2011 by Ken Sakamura.
- * This software is distributed under the latest version of T-License 2.x.
- *----------------------------------------------------------------------
- *
- * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
- * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
- *
- *----------------------------------------------------------------------
- */
-
-/*
- * cpudepend.h
- *
- * ARM-related definitions
- */
-
-#ifndef __MONITOR_ARM_CPUDEPEND_H__
-#define __MONITOR_ARM_CPUDEPEND_H__
-
-#include <machine.h>
-
-/*
- * monitor stack area
- * stack area is from &__stack_top to &__stack_bottom
- * initial stack pointer = &__stack_bottom
- */
-IMPORT UB __stack_top, __stack_bottom;
-
-/*
- * first level page table
- */
-IMPORT UW* const TopPageTable; /* location of page table */
-#define N_PageTableEntry 0x1000 /* number of entries */
-
-/*
- * address conversion to non-cached and cached area
- * in the case of ARM, all address have the same cache mode, and hence
- * return as it is.
- */
-#define NOCACHE_ADDR(p) (p)
-#define CACHE_ADDR(p) (p)
-
-/*
- * I/O port access functions
- */
-Inline void out_w( INT port, UW data )
-{
- *(_UW*)port = data;
-}
-Inline void out_h( INT port, UH data )
-{
- *(_UH*)port = data;
-}
-Inline void out_b( INT port, UB data )
-{
- *(_UB*)port = data;
-}
-
-Inline _UW in_w( INT port )
-{
- return *(_UW*)port;
-}
-Inline UH in_h( INT port )
-{
- return *(_UH*)port;
-}
-Inline UB in_b( INT port )
-{
- return *(_UB*)port;
-}
-
-/*
- * value of control register (r1) of system control coprocessor cp15
- */
-#if CPU_ARM1176
-#define MASK_CACHEMMU (0xFFFFCC78) /* V,I,R,S,C,A,M (B = 0) */
-#define VALID_CACHEMMU (0x3307) /* B = 0 */
-#define DIS_CACHEMMU (0x0000) /* I=0,R=0,S=0,C=0,A=0,M=0 */
-#define DIS_CACHEONLY (0x0001) /* I=0,R=0,S=0,C=0,A=0,M=1 */
-#define ENB_CACHEMMU (0x1007) /* I=1,R=0,S=0,C=1,A=1,M=1 */
-#define ENB_MMUONLY (0x0003) /* I=0,R=0,S=0,C=0,A=1,M=1 */
-#endif
-
-/*
- * references registers under monitor control
- * references the value of registers at the time of monitor entry.
- */
-IMPORT UW getCP15( W reg, W opcd ); /* CP15 register CRn: reg, Op2: opcd */
-IMPORT UW getCurPCX( void ); /* PC register (raw value) */
-IMPORT UW getCurCPSR( void ); /* CPSR register */
-
-#endif /* __MONITOR_ARM_CPUDEPEND_H__ */
diff --git a/tkernel_source/monitor/include/tmonitor.h b/tkernel_source/monitor/include/tmonitor.h
index 46e44bb..1711845 100644
--- a/tkernel_source/monitor/include/tmonitor.h
+++ b/tkernel_source/monitor/include/tmonitor.h
@@ -31,7 +31,7 @@
/* CPU-dependent definitions */
#if CPU_ARM
-# include <mach/cpudepend.h>
+# include <asm/cpudepend.h>
#endif
/*
--
1.9.1
