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Message #00057
[PATCH] mx28: icoll timer fiq test code
From: Du Huanpeng <u74147@xxxxxxxxx>
Signed-off-by: Du Huanpeng <u74147@xxxxxxxxx>
---
.../monitor/hwdepend/arm/cpu/eitent-start.S | 10 ++
.../monitor/hwdepend/arm/mach-mx28/icoll.c | 3 +-
.../monitor/hwdepend/arm/mach-mx28/waitusec.c | 2 +-
tkernel_source/monitor/tmmain/kernel.c | 151 ++++++++++++++++++++-
4 files changed, 163 insertions(+), 3 deletions(-)
diff --git a/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S b/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S
index 1e5ec6d..b493e7e 100644
--- a/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S
+++ b/tkernel_source/monitor/hwdepend/arm/cpu/eitent-start.S
@@ -96,8 +96,13 @@ fiq_entry: @ 1C : FIQ
* no saving of registers to stack is performed.
* the content of R12_fiq(ip) register is overwritten.
*/
+ ldr r0, =fiqmsg
+ bl printk
+
ldr ip, =EIT_ENTRY(EIT_FIQ)
ldr pc, [ip]
+fiqmsg:
+.asciz "FIQ"
__startup_entry:
mov r0, #0
@@ -165,7 +170,12 @@ syscall:
* lr = indeterminate
*/
irq_entry:
+ ldr r0, =irqmsg
+ bl printk
+ b irq_entry
bx lr
+irqmsg:
+.asciz "IRQ"
#ifdef CONFIG_MACH_EM1D
#endif
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c b/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c
index 38b4fd0..3427085 100644
--- a/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c
+++ b/tkernel_source/monitor/hwdepend/arm/mach-mx28/icoll.c
@@ -53,7 +53,8 @@ static void icoll_mask_irq(unsigned int irq)
g_icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq));
}
-static void icoll_unmask_irq(unsigned int irq)
+//static
+ void icoll_unmask_irq(unsigned int irq)
{
w_out(BM_ICOLL_INTERRUPTn_ENABLE,
g_icoll_base + HW_ICOLL_INTERRUPTn_SET(irq));
diff --git a/tkernel_source/monitor/hwdepend/arm/mach-mx28/waitusec.c b/tkernel_source/monitor/hwdepend/arm/mach-mx28/waitusec.c
index 41e1146..25b0635 100644
--- a/tkernel_source/monitor/hwdepend/arm/mach-mx28/waitusec.c
+++ b/tkernel_source/monitor/hwdepend/arm/mach-mx28/waitusec.c
@@ -60,7 +60,7 @@ EXPORT void waitMsec(UW msec)
*/
EXPORT void setupWaitUsec(void)
{
- delay64us = 64*2;
+ delay64us = 256;
printk("%s:%s\n", __FILE__, __func__);
return ;
}
diff --git a/tkernel_source/monitor/tmmain/kernel.c b/tkernel_source/monitor/tmmain/kernel.c
index 1a0f61c..3abf1bd 100644
--- a/tkernel_source/monitor/tmmain/kernel.c
+++ b/tkernel_source/monitor/tmmain/kernel.c
@@ -7,6 +7,10 @@ int get_cpsr(void);
extern int getr(int *);
extern int syscall(int);
+void start_timer(unsigned r0, unsigned r1, unsigned r2, unsigned r3);
+
+void icoll_unmask_irq(unsigned int irq);
+
int start_kernel(int argc, char *argv[])
{
@@ -14,16 +18,27 @@ int start_kernel(int argc, char *argv[])
int rc;
int reg[16];
int cpsr;
+ const int timer_irq = 49;
cpsr = get_cpsr();
cpsr &= ~(1<<6 | 1<<7); /* enable irq & fiq */
cpsr = set_cpsr(cpsr);
- printk("starting kernel...");
+ printk("starting kernel...\n");
+ printk("starting timer1...\n");
avic_init_irq((void *)0x80000000, 128);
+ mxs_enable_fiq_functionality(1);
+
+ icoll_unmask_irq(timer_irq);
+
+
+
+ start_timer(0, 0, 0, 0);
+ waitMsec(1000);
+
printk("CPSR: [%08X]\n", getcpsr());
getr(reg);
@@ -31,6 +46,140 @@ int start_kernel(int argc, char *argv[])
printk("register [%d]: [%X]\n", i, reg[i]);
}
printk("Hello World!\n");
+
+ while(1) {
+ printk("E");
+ waitMsec(1000);
+ }
return 0;
}
+
+/* Test stuff for i.MX280 only */
+
+/* ICOLL */
+#define HW_ICOLL_VECTOR 0x80000000
+#define HW_ICOLL_LEVELACK 0x80000010
+#define HW_ICOLL_CTRL 0x80000020
+#define HW_ICOLL_VBASE 0x80000040
+#define HW_ICOLL_STAT 0x80000070
+#define HW_ICOLL_RAW0 0x800000A0
+#define HW_ICOLL_RAW1 0x800000B0
+#define HW_ICOLL_RAW2 0x800000C0
+#define HW_ICOLL_RAW3 0x800000D0
+
+struct HW_TIMROT_T {
+ unsigned long HW_TIMROT_ROTCTRL[4];
+ unsigned long HW_TIMROT_TIMCTRL[4];
+ unsigned long HW_TIMROT_RUNNING_COUNT[4];
+ unsigned long HW_TIMROT_FIXED_COUNT[4];
+ unsigned long HW_TIMROT_MATCH_COUNT[4];
+};
+
+#define IRQ (1<<15)
+#define IRQ_EN (1<<14)
+#define MATCH_MODE (1<<11)
+#define POLARITY (1<<8)
+#define UPDATA (1<<7)
+#define RELOAD (1<<6)
+#define PRESCALE(n) ((n)<<4)
+ #define IDV_BY_8 (0x3)
+#define SELECT(n) ((n)<<0)
+ #define TICK_ALWAYS (0XF)
+
+
+
+volatile struct HW_TIMROT_T *hw_timer_rotary[3];
+
+int hw_icoll_raw(int irq)
+{
+ int irq_raw[4];
+
+ irq_raw[0] = in_w(HW_ICOLL_RAW0);
+ irq_raw[1] = in_w(HW_ICOLL_RAW1);
+ irq_raw[2] = in_w(HW_ICOLL_RAW2);
+ irq_raw[3] = in_w(HW_ICOLL_RAW3);
+
+ return irq_raw[irq/32] & (1 << (irq%32));
+
+}
+
+void do_irq_timer(unsigned r0, unsigned r1, unsigned r2, unsigned r3)
+{
+}
+
+void start_timer(unsigned r0, unsigned r1, unsigned r2, unsigned r3)
+{
+ int val;
+ int i;
+
+#define BIT(n) (1<<n)
+#define BITTST(val, n) ((val) & BIT(n))
+
+ hw_timer_rotary[0] = (void *)(0x80068000); /* have ROTCTRL */
+ hw_timer_rotary[1] = (void *)(0x80068050);
+ hw_timer_rotary[2] = (void *)(0x80068080);
+ hw_timer_rotary[3] = (void *)(0x800680C0);
+
+ val = hw_timer_rotary[0]->HW_TIMROT_ROTCTRL[0];
+ printk("This SoC has:\n");
+ if(BITTST(val,25)) printk("timer 0\n");
+ if(BITTST(val,26)) printk("timer 1\n");
+ if(BITTST(val,27)) printk("timer 2\n");
+ if(BITTST(val,28)) printk("timer 3\n");
+
+#define IRQ (1<<15)
+#define IRQ_EN (1<<14)
+#define MATCH_MODE (1<<11)
+#define POLARITY (1<<8)
+#define UPDATA (1<<7)
+#define RELOAD (1<<6)
+#define PRESCALE(n) ((n)<<4)
+ #define DIV_BY_8 (0x3)
+#define SELECT(n) ((n)<<0)
+ #define TICK_ALWAYS (0XF)
+
+
+#define SET 1
+#define CLR 2
+#define TOG 3
+
+ hw_timer_rotary[1]->HW_TIMROT_FIXED_COUNT[0] = 0x00001000;
+ val = IRQ_EN | UPDATA | PRESCALE(TICK_ALWAYS) | SELECT(0xB);
+ hw_timer_rotary[1]->HW_TIMROT_TIMCTRL[0] = val;
+ hw_timer_rotary[1]->HW_TIMROT_TIMCTRL[SET] = RELOAD;
+
+
+ for(i=0; i<30; i++) {
+ val = (unsigned long)&(hw_timer_rotary[1]->HW_TIMROT_RUNNING_COUNT[0]);
+ printk("Reading register [%016x]:\n", val);
+ printk("Reading register [% 16x]:\n", val);
+ printk("Reading register [%-16x]:\n", val);
+ printk("Reading register [%116x]:\n", val);
+
+ val = (hw_timer_rotary[1]->HW_TIMROT_RUNNING_COUNT[0]);
+
+ printk("%08X\n", val);
+
+ printk("ICOLL RAW:\n"
+ "%033b %033b\n"
+ "%033b %033b\n",
+ in_w(HW_ICOLL_RAW0),
+ in_w(HW_ICOLL_RAW1),
+ in_w(HW_ICOLL_RAW2),
+ in_w(HW_ICOLL_RAW3));
+
+ printk("hw_icoll_raw[%d][%d]\n", 49, !!hw_icoll_raw(49));
+
+ waitMsec(300);
+
+
+
+ }
+
+ printk("Goodbye TIMER!\n");
+
+
+}
+
+
--
1.9.1
