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Message #00068
[PATCH] tkernel: arm, prepare port for mx28(arm926ej-s)
From: Du Huanpeng <u74147@xxxxxxxxx>
Signed-off-by: Du Huanpeng <u74147@xxxxxxxxx>
---
.../sysdepend/arm/mach-mx28/cache_info.h | 55 ++++++
tkernel_source/sysdepend/arm/mach-mx28/cntwus.c | 97 +++++++++++
tkernel_source/sysdepend/arm/mach-mx28/devinit.c | 185 +++++++++++++++++++++
tkernel_source/sysdepend/arm/mach-mx28/icrt0.S | 103 ++++++++++++
tkernel_source/sysdepend/arm/mach-mx28/icrt0_ram.S | 113 +++++++++++++
tkernel_source/sysdepend/arm/mach-mx28/patch.c | 57 +++++++
tkernel_source/sysdepend/arm/mach-mx28/patch.h | 30 ++++
tkernel_source/sysdepend/arm/mach-mx28/power.c | 36 ++++
.../sysdepend/arm/mach-mx28/tkdev_conf.h | 148 +++++++++++++++++
.../sysdepend/arm/mach-mx28/tkdev_init.c | 86 ++++++++++
.../sysdepend/arm/mach-mx28/tkdev_timer.h | 185 +++++++++++++++++++++
11 files changed, 1095 insertions(+)
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/cache_info.h
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/cntwus.c
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/devinit.c
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/icrt0.S
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/icrt0_ram.S
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/patch.c
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/patch.h
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/power.c
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/tkdev_conf.h
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/tkdev_init.c
create mode 100644 tkernel_source/sysdepend/arm/mach-mx28/tkdev_timer.h
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/cache_info.h b/tkernel_source/sysdepend/arm/mach-mx28/cache_info.h
new file mode 100644
index 0000000..fa0ddce
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/cache_info.h
@@ -0,0 +1,55 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * cache_info.h (EM1-D512)
+ * Cache Information
+ */
+
+#ifndef _CACHE_INFO_
+#define _CACHE_INFO_
+
+/*
+ * Set non-cache area memory
+ * When using the control table for non-cache area memory
+ * by memory manager routines, define the address of non-cache area.
+ *
+ * When not using, specify 0 for UseNoCacheMemoryTable.
+ */
+#define USE_NOCACHE_MEMTBL (0) /* Do not use */
+
+#define NoCacheMemoryTop (0) /* Top address of non-cache area */
+#define NoCacheMemoryEnd (0) /* End address of non-cache area */
+
+/*
+ * Conversion between page number and address
+ * When switching ON/Off of cache by an address,
+ * define the conversion formula for the following Macro:
+ */
+#define CachingAddr(p) (p) /* Do not convert */
+#define NoCachingAddr(p) (p)
+
+/*
+ * Conversion between physical address and logical address of
+ * real memory area (physical space)
+ */
+#define toLogicalAddress(paddr) (void*)(paddr)
+#define toPhysicalAddress(laddr) (void*)(laddr)
+
+/*
+ * Convert logical address into logical address of the cache off area
+ */
+#define toNoCacheLogicalAddress(laddr) (void*)(laddr)
+
+#endif /* _CACHE_INFO_ */
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/cntwus.c b/tkernel_source/sysdepend/arm/mach-mx28/cntwus.c
new file mode 100644
index 0000000..b49aaef
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/cntwus.c
@@ -0,0 +1,97 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * Calculate the value of required count for loop-wait for a given period (in micro seconds)
+ */
+
+#include <basic.h>
+#include <sys/sysinfo.h>
+#include <tk/syslib.h>
+#include "tkdev_conf.h"
+
+/*
+ * Loop wait
+ * disable the inline expansion caused by compiler optimization to obtain accurate
+ * measurement.
+ */
+__attribute__ ((noinline))
+LOCAL void WaitLoop( UW count )
+{
+ Asm(" _loop: subs %0, %0, #1 \n"
+ " bhi _loop "
+ : "=r"(count)
+ : "0"(count + 1)
+ );
+}
+
+/*
+ * WaitUsec() calculate the loop count for a given time (in microseconds)
+ * interrupt-disabled state is assumed.
+ */
+EXPORT void CountWaitUsec( void )
+{
+ UW t0, t1, t2;
+ UW cnt;
+ UW d;
+
+ /* stop timer */
+ out_w(TI_OP, 0);
+
+ /* select clock */
+ out_w(TI0TIN_SEL, (in_w(TI0TIN_SEL) & ~3) | TITIN_PLL3);
+
+ /* supply clock */
+ out_w(GCLKCTRL3ENA, in_w(GCLKCTRL3ENA) | TI0_TIN_GCK);
+ out_w(GCLKCTRL3, in_w(GCLKCTRL3) | TI0_TIN_GCK);
+
+ /* enable timer */
+ out_w(TI_OP, TM_EN);
+ while ( (in_w(TI_SCLR) & TM_SCLR) != 0 );
+ WaitLoop(100);
+
+ /* set counter */
+ out_w(TI_SET, 0xffffffff);
+
+ /* start timer counting */
+ out_w(TI_OP, TSTART|TM_EN);
+
+ WaitLoop(100); /* wait for a little (just in case) */
+
+ /* measurement */
+ t0 = in_w(TI_RCR);
+ WaitLoop(1001);
+ t1 = in_w(TI_RCR);
+ WaitLoop(21001);
+ t2 = in_w(TI_RCR);
+
+ /* stop timer */
+ out_w(TI_OP, 0);
+
+ /* stop clock */
+ out_w(GCLKCTRL3, in_w(GCLKCTRL3) & ~TI0_TIN_GCK);
+
+ /* the time for 20000 loops is calculated excluding the
+ overhead for the rest of measurement time. */
+ cnt = (t2 - t1) - (t1 - t0);
+
+ /* Calculate the loop count that spends 64 microseconds
+ * 20000 loops
+ * loop64us = ---------------------- * 64usec
+ * cnt * (1 / TIN_CLK)
+ * TIN_CLK = input clock to the timer [Hz]
+ */
+ d = in_w(DIVTIMTIN);
+ SCInfo.loop64us = TIN_CLK(d) / (cnt * (50/2)) * (64/2);
+}
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/devinit.c b/tkernel_source/sysdepend/arm/mach-mx28/devinit.c
new file mode 100644
index 0000000..4ef3bd0
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/devinit.c
@@ -0,0 +1,185 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by T-Engine Forum at 2014/09/10.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * devinit.c (EM1-D512)
+ * Device-Dependent Initialization
+ */
+
+#include "sysinit.h"
+#include "kernel.h"
+#include <tk/sysdef.h>
+#include <sys/sysinfo.h>
+#include <sys/rominfo.h>
+#include <sys/util.h>
+#include <device/devconf.h>
+#include <libstr.h>
+
+/*
+ * Display the progress of start processing
+ * 0x10 - 0x1F : Initialization (before kernel starts)
+ * 0x20 - 0x2F : Kernel start processing
+ * 0x30 - 0x3F : Start processing (after kernel starts)
+ */
+EXPORT void DispProgress( W n )
+{
+}
+
+/* ------------------------------------------------------------------------ */
+
+/*
+ * Initialization at ROM startup
+ * This function is called before 'main()'.
+ * (same as 'SBOOT' for disk boot)
+ */
+EXPORT ER ROM_startup( void )
+{
+ W val[L_DEVCONF_VAL];
+ W n;
+
+ /* Set SYSCONF/DEVCONF */
+ SCInfo.sysconf = ROMInfo->sysconf;
+ SCInfo.devconf = ROMInfo->devconf;
+
+ /* Set debug mode */
+ n = GetDevConf(DCTAG_DEBUGMODE, val);
+ SCInfo.bm.c.debug = ( n >= 1 && val[0] > 0 )? 1: 0;
+
+ /* Set boot device (no boot device) */
+ SCInfo.bootdev[0] = '\0';
+
+ return E_OK;
+}
+
+/*
+ * Set stack by exception mode
+ */
+LOCAL void setExcStack( UW mode, UW stack )
+{
+ Asm(" msr cpsr_c, %1 \n"
+ " mov sp, %0 \n"
+ " msr cpsr_c, %2 "
+ :: "l"(stack), "r"(mode|PSR_I|PSR_F), "i"(PSR_SVC|PSR_I|PSR_F));
+}
+
+/*
+ * Initialization before T-Kernel starts
+ */
+#define SYSCONF_VAL_MAX (16)
+
+EXPORT ER init_device( void )
+{
+IMPORT void CountWaitUsec( void ); /* cntwus.c */
+
+/* Low level memory manager information */
+IMPORT UW lowmem_top;
+
+ W n, v[SYSCONF_VAL_MAX];
+
+ /* Compute loop count of micro second wait */
+ CountWaitUsec();
+
+ /* Set stack for each exception mode */
+ lowmem_top = (lowmem_top + 3) & ~0x00000003U; /* Alignment match */
+ n = GetSysConf(SCTAG_ABTSTKSZ, v); /* Abort (MMU) */
+ n = ( n < 1 )? 64: v[0];
+ lowmem_top += (n + 3) & ~0x00000003U;
+ setExcStack(PSR_ABT, lowmem_top);
+
+ n = GetSysConf(SCTAG_UNDSTKSZ, v); /* Undefined order exception */
+ n = ( n < 1 )? 64: v[0];
+ lowmem_top += (n + 3) & ~0x00000003U;
+ setExcStack(PSR_UND, lowmem_top);
+
+ n = GetSysConf(SCTAG_IRQSTKSZ, v); /* Interrupt (IRQ) */
+ n = ( n < 1 )? 512: v[0];
+ lowmem_top += (n + 3) & ~0x00000003U;
+ setExcStack(PSR_IRQ, lowmem_top);
+
+ n = GetSysConf(SCTAG_FIQSTKSZ, v); /* Fast interrupt (FIQ) */
+ n = ( n < 1 )? 128: v[0];
+ lowmem_top += (n + 3) & ~0x00000003U;
+ setExcStack(PSR_FIQ, lowmem_top);
+
+ return E_OK;
+}
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Start processing after T-Kernel starts
+ * Called from the initial task contexts.
+ */
+EXPORT ER start_device( void )
+{
+ return E_OK;
+}
+
+/* ------------------------------------------------------------------------ */
+/*
+ * System finalization
+ * Called just before system shutdown.
+ * Execute finalization that must be done before system shutdown.
+ */
+EXPORT ER finish_device( void )
+{
+ return E_OK;
+}
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Re-starting processing
+ */
+
+/*
+ * Re-starting processing
+ * mode = -1 Reset and re-start (cold boot)
+ * mode = -2 Re-start (warm boot)
+ * mode = -3 Reboot (normal boot)
+ * mode = 0xFFhhmmss Re-start at hh:mm:ss
+ * 0 <= hh < 24, 0 <= mm,ss < 60
+ */
+EXPORT ER restart_device( W mode )
+{
+ if ( mode == -1 ) {
+ /* Reset and re-start (cold boot) */
+#if USE_KERNEL_MESSAGE
+ tm_putstring((UB*)"\n<< SYSTEM RESTART >>\n");
+#endif
+ tm_exit(-1); /* no return */
+ return E_OBJ;
+ }
+
+ if ( mode == -3 ) {
+ /* Reboot (normal boot) */
+ UB bdcmd[4 + L_DEVNM] = "bd ";
+#if USE_KERNEL_MESSAGE
+ tm_putstring((UB*)"\n<< SYSTEM REBOOT >>\n");
+#endif
+ STRNCAT((char*)bdcmd, (char*)SCInfo.bootdev, L_DEVNM);
+ tm_command(bdcmd); /* Normally no return */
+ return E_OBJ; /* When the BD command is an error */
+ }
+
+ if ( mode == -2 ) {
+ return E_NOSPT; /* Unsupported */
+ }
+
+ if ( (mode & 0xff000000) == 0xff000000 ) {
+ /* Re-start at specified time */
+ return E_NOSPT; /* Unsupported */
+ }
+
+ return E_PAR;
+}
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/icrt0.S b/tkernel_source/sysdepend/arm/mach-mx28/icrt0.S
new file mode 100644
index 0000000..79d2363
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/icrt0.S
@@ -0,0 +1,103 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * icrt0.S (EM1-D512)
+ * System Startup
+ */
+
+#include <machine.h>
+#include <tk/asm.h>
+
+#if _Csym == 0
+#define START _start
+#else
+#define START start
+#endif
+
+ /* Low level memory manager information */
+ .comm Csym(lowmem_top), 4 // Head of area (Low address)
+ .comm Csym(lowmem_limit), 4 // End of area (High address)
+
+ .lcomm monitor_stacktop, 4 // Monitor stack pointer for re-startup
+
+#define SYSINFO 0x30004400 // System common information
+#define RAM_TOP (SYSINFO + 0) // Head of ext. RAM free area
+#define RAM_END (SYSINFO + 4) // End of ext. RAM free area
+
+ .text
+ .balign 4
+ .globl START
+ .type START, %function
+START:
+ /* Use the stack set by the monitor */
+ ldr ip, =PSR_SVC|PSR_DI|PSR_F // SVC mode/Interrupt disable
+ msr cpsr_xc, ip
+
+ /* MMU is already ON. The initial setting is done.
+ Only cache should be ON */
+ mrc p15, 0, r4, cr1, c0
+ orr r4, r4, #CR1_C
+ orr r4, r4, #CR1_I|CR1_Z
+ mcr p15, 0, r4, cr1, c0
+ ldr r4, =0
+ mcr p15, 0, r4, cr7, c7, 0 // Cache flush
+
+ ldr r5, =__data_org // Initialization of 'data' area (ROM startup)
+ ldr r6, =__data_start
+ subs r10, r5, r6 // If r10 != 0, start Rom
+ beq nocopy_data
+ ldr r7, =_edata
+ cmp r6, r7
+ bhs nocopy_data
+ copy_data:
+ ldr r4, [r5], #4
+ str r4, [r6], #4
+ cmp r6, r7
+ blo copy_data
+ nocopy_data:
+
+ ldr r4, =0 // Clear 'bss' area
+ ldr r5, =__bss_start
+ ldr r6, =_end
+ cmp r5, r6
+ bhs nobss
+ clrbss:
+ str r4, [r5], #4
+ cmp r5, r6
+ blo clrbss
+ nobss:
+
+ ldr ip, =monitor_stacktop // Monitor stack pointer for re-startup
+ str sp, [ip] // Save
+ bic sp, sp, #7 // align stack modulo 8 bytes.
+
+ ldr ip, =RAM_TOP // Low level memory manager initial setting
+ ldr r5, [ip]
+ cmp r6, r5 // _end or RAM_TOP
+ movhi r5, r6 // Either of High addresses
+ ldr ip, =lowmem_top
+ str r5, [ip] // lowmem_top = _end or RAM_TOP
+ ldr ip, =RAM_END
+ ldr r5, [ip]
+ ldr ip, =lowmem_limit
+ str r5, [ip] // lowmem_limit = RAM_END
+
+ cmp r10, #0
+ blne Csym(ROM_startup) // Initialization at ROM startup
+
+ bl Csym(main) // System startup
+
+ l_end: // Not suppose to return from 'main,'
+ b l_end // but, just in case, prepare for out of control.
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/icrt0_ram.S b/tkernel_source/sysdepend/arm/mach-mx28/icrt0_ram.S
new file mode 100644
index 0000000..36a1609
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/icrt0_ram.S
@@ -0,0 +1,113 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * icrt0_ram.S (EM1-D512)
+ * System Startup
+ */
+
+#include <machine.h>
+#include <tk/asm.h>
+
+#if _Csym == 0
+#define START _start
+#else
+#define START start
+#endif
+
+ /* Low level memory manager information */
+ .comm Csym(lowmem_top), 4 // Head of area (Low address)
+ .comm Csym(lowmem_limit), 4 // End of area (High address)
+
+ .lcomm monitor_stacktop, 4 // Monitor stack pointer for re-startup
+
+#define SYSINFO 0x30004400 // System common information
+#define RAM_TOP (SYSINFO + 0) // Head of ext. RAM free area
+#define RAM_END (SYSINFO + 4) // End of ext. RAM free area
+#define SYSCONF (SYSINFO + 8) // SYSCONF top
+
+ .text
+ .balign 4
+ .globl START
+ .type START, %function
+START:
+ /* Use the stack set by the monitor */
+ ldr ip, =PSR_SVC|PSR_DI|PSR_F // SVC mode/Interrupt disable
+ msr cpsr_xc, ip
+
+ /* MMU is already ON. The initial setting is done.
+ Only cache should be ON */
+ mrc p15, 0, r4, cr1, c0
+ orr r4, r4, #CR1_C
+ orr r4, r4, #CR1_I|CR1_Z
+ mcr p15, 0, r4, cr1, c0
+ ldr r4, =0
+ mcr p15, 0, r4, cr7, c7, 0 // Cache flush
+
+ ldr r5, =__data_org // Initialization of 'data' area (ROM startup)
+ ldr r6, =__data_start
+ subs r10, r5, r6 // If r10 != 0, start Rom
+ beq nocopy_data
+ ldr r7, =_edata
+ cmp r6, r7
+ bhs nocopy_data
+ copy_data:
+ ldr r4, [r5], #4
+ str r4, [r6], #4
+ cmp r6, r7
+ blo copy_data
+ nocopy_data:
+
+ ldr r4, =0 // Clear 'bss' area
+ ldr r5, =__bss_start
+ ldr r6, =_end
+ cmp r5, r6
+ bhs nobss
+ clrbss:
+ str r4, [r5], #4
+ cmp r5, r6
+ blo clrbss
+ nobss:
+
+ ldr ip, =monitor_stacktop // Monitor stack pointer for re-startup
+ str sp, [ip] // Save
+ bic sp, sp, #7 // align stack module 8 bytes
+
+ ldr ip, =RAM_TOP // Low level memory manager initial setting
+ ldr r5, [ip]
+ cmp r6, r5 // _end or RAM_TOP
+ movhi r5, r6 // Either of High addresses
+ ldr ip, =lowmem_top
+ str r5, [ip] // lowmem_top = _end or RAM_TOP
+ ldr ip, =RAM_END
+ ldr r5, [ip]
+ ldr ip, =lowmem_limit
+ str r5, [ip] // lowmem_limit = RAM_END
+
+ ldr r4, =SYSCONF
+ ldr r5, [r4]
+ cmp r5, #0
+ bleq l1
+
+ cmp r10, #0
+ bleq l2
+
+ l1:
+ bl Csym(ROM_startup) // Initialization at ROM startup
+
+ l2:
+ bl Csym(main) // System startup
+
+ l_end: // Not suppose to return from 'main,'
+ b l_end // but, just in case, prepare for out of control.
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/patch.c b/tkernel_source/sysdepend/arm/mach-mx28/patch.c
new file mode 100644
index 0000000..15e9e3d
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/patch.c
@@ -0,0 +1,57 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * patch.c (EM1-D512)
+ * System-dependent initialize process
+ */
+
+#include <basic.h>
+#include <tk/tkernel.h>
+#include "patch.h"
+
+#if USE_SYSDEPEND_PATCH1
+/*
+ * Empty handler to ignore stray interrupts
+ */
+LOCAL void ignore_interrupt( UINT dintno )
+{
+static INT ignore_interrupt_counter;
+
+ ignore_interrupt_counter++;
+}
+
+/*
+ * System-dependent processes (before start_system)
+ */
+EXPORT void sysdepend_patch1( void )
+{
+ T_DINT dint;
+
+ /* register an empty handler to ignore stray interrupts */
+ dint.intatr = TA_HLNG;
+ dint.inthdr = ignore_interrupt;
+ tk_def_int(DINTNO(IV_IRQ(95)), &dint);
+}
+#endif
+
+#if USE_SYSDEPEND_PATCH2
+/*
+ * System-dependent processes (after start_system)
+ */
+EXPORT void sysdepend_patch2( void )
+{
+ /* Do nothing */
+}
+#endif
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/patch.h b/tkernel_source/sysdepend/arm/mach-mx28/patch.h
new file mode 100644
index 0000000..2092d34
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/patch.h
@@ -0,0 +1,30 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * patch.h (EM1-D512)
+ * System-dependent initialize process
+ */
+
+#ifndef _PATCH_
+#define _PATCH_
+
+/* Define '1' when using patch processes */
+#define USE_SYSDEPEND_PATCH1 1
+#define USE_SYSDEPEND_PATCH2 0
+
+EXPORT void sysdepend_patch1( void );
+EXPORT void sysdepend_patch2( void );
+
+#endif /* _PATCH_ */
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/power.c b/tkernel_source/sysdepend/arm/mach-mx28/power.c
new file mode 100644
index 0000000..685684c
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/power.c
@@ -0,0 +1,36 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * power.c (EM1-D512)
+ * Power-Saving Function
+ */
+
+#include "sysmgr.h"
+
+/*
+ * Switch to power-saving mode
+ */
+EXPORT void low_pow( void )
+{
+ Asm("mcr p15, 0, %0, cr7, c0, 4":: "r"(0));
+}
+
+/*
+ * Move to suspend mode
+ */
+EXPORT void off_pow( void )
+{
+ Asm("mcr p15, 0, %0, cr7, c0, 4":: "r"(0));
+}
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/tkdev_conf.h b/tkernel_source/sysdepend/arm/mach-mx28/tkdev_conf.h
new file mode 100644
index 0000000..c9703f6
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/tkdev_conf.h
@@ -0,0 +1,148 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * tkdev_conf.h (EM1-D512)
+ * Target System Configuration
+ */
+
+#ifndef _TKDEV_CONF_
+#define _TKDEV_CONF_
+/* Also included from assembler source */
+
+/*
+ * Timer
+ * register size W
+ */
+#define TI(n) ( 0xc0000000 + (n) ) /* TI0 */
+
+#define TI_OP TI(0x00) /* RW timer operation */
+#define TI_CLR TI(0x04) /* -W clear timer */
+#define TI_SET TI(0x08) /* RW set timer value */
+#define TI_RCR TI(0x0c) /* R- current counter */
+#define TI_SCLR TI(0x14) /* RW watch out for setting timer value */
+
+#define TO_EN 0x0004 /* enable TOUT */
+#define TSTART 0x0002 /* start counting */
+#define TM_EN 0x0001 /* enable timer */
+
+#define TCR_CLR 0x0002 /* clear counter */
+
+#define TM_SCLR 0x0001 /* watch out for setting timer value */
+
+/*
+ * Supply clock
+ * register size W
+ */
+#define ASMU(n) ( 0xc0110000 + (n) )
+
+#define TI0TIN_SEL ASMU(0x0138) /* set TI0/TW0 TIN */
+#define DIVTIMTIN ASMU(0x014c) /* set timer clock divisor */
+#define GCLKCTRL3 ASMU(0x01cc) /* set clock gate */
+#define GCLKCTRL3ENA ASMU(0x01d0) /* enable write */
+
+#define TITIN_PLL3 0 /* PLL3 divided by DIVTIMTIN */
+#define TITIN_32768 1 /* 32.768 KHz */
+#define TITIN_32K 2 /* 32 KHz */
+
+#define TI0_TIN_GCK 0x00000001 /* TI0 TIN gate */
+
+/*
+ * Input clock
+ * PLL3 divided by DIVTIMTIN
+ */
+#define PLL3_CLK 229376000 /* Hz */
+
+#define D0(d) ( (d) & 0x7 ) /* DIV0TIMTIN */
+#define D1(d) ( ((d) >> 4) & 0xf ) /* DIV1TIMTIN */
+
+#define TIN_CLK(d) ( PLL3_CLK / ((1 << D0(d)) * (D1(d) + 1)) )
+
+/*
+ * TI0 timer interrupt
+ */
+#define IRQ_TIMER 54 /* IRQ number */
+#define VECNO_TIMER ( EIT_IRQ(IRQ_TIMER) ) /* interrupt vector number */
+
+#define IRQM(irq) ( 1 << ((irq) % 32) ) /* IRQ bit mask */
+
+/*
+ * Interrupt controller
+ * register size W
+ */
+#define AINT(n) ( 0xc0020000 + (n) ) /* ACPU Interrupt */
+#define SINT(n) ( 0xcc010000 + (n) ) /* ACPU Secure Interrupt */
+
+#define IT0_IEN0 AINT(0x0000) /* RW ACPU interrupt enable 0 */
+#define IT0_IEN1 AINT(0x0004) /* RW ACPU interrupt enable 1 */
+#define IT0_IEN2 AINT(0x0100) /* RW ACPU interrupt enable 2 */
+#define IT0_IDS0 AINT(0x0008) /* -W ACPU interrupt disable 0 */
+#define IT0_IDS1 AINT(0x000C) /* -W ACPU interrupt disable 1 */
+#define IT0_IDS2 AINT(0x0104) /* -W ACPU interrupt disable 2 */
+#define IT0_RAW0 AINT(0x0010) /* R- ACPU interrupt Raw status 0 */
+#define IT0_RAW1 AINT(0x0014) /* R- ACPU interrupt Raw status 1 */
+#define IT0_RAW2 AINT(0x0108) /* R- ACPU interrupt Raw status 2 */
+#define IT0_MST0 AINT(0x0018) /* R- ACPU interrupt mask / status 0 */
+#define IT0_MST1 AINT(0x001C) /* R- ACPU interrupt mask / status 1 */
+#define IT0_MST2 AINT(0x010C) /* R- ACPU interrupt mask / status 2 */
+#define IT0_IIR AINT(0x0024) /* -W ACPU interrupt status / reset */
+#define IT0_FIE AINT(0x0080) /* RW ACPU FIQ enable interrupt */
+#define IT0_FID AINT(0x0084) /* -W ACPU FIQ disable interrupt */
+#define IT_PINV_SET0 AINT(0x0300) /* RW enable inverted logic for interrupt input 0 */
+#define IT_PINV_SET1 AINT(0x0304) /* RW enable inverted logic for interrupt input 1 */
+#define IT_PINV_SET2 AINT(0x0308) /* RW enable inverted logic for interrupt input 2 */
+#define IT_PINV_CLR0 AINT(0x0310) /* -W disable inverted logic for interrupt input 0 */
+#define IT_PINV_CLR1 AINT(0x0314) /* -W disable inverted logic for interrupt input 1 */
+#define IT_PINV_CLR2 AINT(0x0318) /* -W disable inverted logic for interrupt input 2 */
+#define IT_LIIS AINT(0x0320) /* -W internal interrupt status / set */
+#define IT_LIIR AINT(0x0324) /* -W internal interrupt status / reset */
+
+#define IT0_IENS0 SINT(0xE200) /* RW ACPU Secure enable interrupt 0 */
+#define IT0_IENS1 SINT(0xE204) /* RW ACPU Secure enable interrupt 1 */
+#define IT0_IENS2 SINT(0xE208) /* RW ACPU Secure enable interrupt 2 */
+#define IT0_IDSS0 SINT(0xE20C) /* -W ACPU Secure disable interrupt 0 */
+#define IT0_IDSS1 SINT(0xE210) /* -W ACPU Secure disable interrupt 1 */
+#define IT0_IDSS2 SINT(0xE214) /* -W ACPU Secure disable interrupt 2 */
+
+/*
+ * GIO interrupt
+ * register size W
+ */
+#define GIO(b, n) ( (b) + (n) ) /* General I/O */
+#define _L ( 0xc0050000 + 0x000 )
+#define _H ( 0xc0050000 + 0x040 )
+#define _HH ( 0xc0050000 + 0x080 )
+#define _HHH ( 0xc0050000 + 0x200 )
+
+#define GIO_IIA(b) GIO(b,0x0014) /* RW enable interrupt ??? */
+#define GIO_IEN(b) GIO(b,0x0018) /* -W enable interrupt */
+#define GIO_IDS(b) GIO(b,0x001C) /* -W disable interrupt */
+#define GIO_IIM(b) GIO(b,0x001C) /* R- enable interrupt ??? */
+#define GIO_RAW(b) GIO(b,0x0020) /* R- interrupt Raw status */
+#define GIO_MST(b) GIO(b,0x0024) /* R- interrupt mask / status */
+#define GIO_IIR(b) GIO(b,0x0028) /* -W reset the cause of interrupt */
+#define GIO_GSW(b) GIO(b,0x003C) /* RW connected to GIO_INT_FIQ pin */
+#define GIO_IDT(n,b) GIO(b,0x0100+(n)*4) /* RW interrupt detection method 0-3 */
+#define GIO_RAWBL(b) GIO(b,0x0110) /* R- edge-triggered interrupt status L */
+#define GIO_RAWBH(b) GIO(b,0x0114) /* R- edge-triggered interrupt status H */
+#define GIO_IRBL(b) GIO(b,0x0118) /* -W clear the cause of edge-triggered interrupt L */
+#define GIO_IRBH(b) GIO(b,0x011C) /* -W clear the cause of edge-tirggered interrupt H */
+
+/*
+ * Timer interrupt level
+ * No meaning since EM1-D512 does not have a mechanism of prioritized interrupt.
+ */
+#define TIMER_INTLEVEL 0
+
+#endif /* _TKDEV_CONF_ */
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/tkdev_init.c b/tkernel_source/sysdepend/arm/mach-mx28/tkdev_init.c
new file mode 100644
index 0000000..16f7caa
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/tkdev_init.c
@@ -0,0 +1,86 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * tkdev_init.c (EM1-D512)
+ * T-Kernel Device-Dependent Initialization/Finalization
+ */
+
+#include "kernel.h"
+#include <tk/sysdef.h>
+#include <tk/syslib.h>
+#include <tm/tmonitor.h>
+#include "tkdev_conf.h"
+
+/*
+ * Target system-dependent initialization
+ */
+EXPORT ER tkdev_initialize( void )
+{
+static UINT giob[4] = { _L, _H, _HH, _HHH };
+ UINT gb;
+ INT i;
+
+ /* initialize GPIO interrupt */
+ for ( i = 0; i < 4; ++i ) {
+ gb = giob[i];
+ out_w(GIO_IDS(gb), 0xffffffff); /* disable interrupt */
+ out_w(GIO_IIA(gb), 0x00000000); /* disassert interrupt pin */
+ out_w(GIO_GSW(gb), 0x00000000); /* disassert FIQ pin */
+ }
+
+ /* initialize interrupt controller (AINT) */
+ out_w(IT0_IDSS0, 0xffffffff); /* disassert interrupt pin */
+ out_w(IT0_IDSS1, 0xffffffff);
+ out_w(IT0_IDSS2, 0xffffffff);
+ out_w(IT0_IDS0, 0xffffffff); /* disable interrupt */
+ out_w(IT0_IDS1, 0xffffffff);
+ out_w(IT0_IDS2, 0xffffffff);
+ out_w(IT_PINV_CLR0, 0xffffffff); /* reset inverted logic */
+ out_w(IT_PINV_CLR1, 0xffffffff);
+ out_w(IT_PINV_CLR2, 0xffffffff);
+ out_w(IT_LIIR, 0xffffffff); /* clear interrupt */
+ out_w(IT0_IIR, 0xffffffff);
+ out_w(IT0_FIE, 0x00000001); /* enable FIQ */
+
+ /* enable GPIO interrupt on AINT */
+ out_w(IT0_IENS0, IRQM(26)|IRQM(27)); /* assert interrupt pin */
+ out_w(IT0_IENS1, IRQM(50)|IRQM(51)|IRQM(52)|IRQM(53));
+ out_w(IT0_IENS2, IRQM(79)|IRQM(80));
+ out_w(IT0_IEN0, IRQM(26)|IRQM(27)); /* enable interrupt */
+ out_w(IT0_IEN1, IRQM(50)|IRQM(51)|IRQM(52)|IRQM(53));
+ out_w(IT0_IEN2, IRQM(79)|IRQM(80));
+
+ /* enable abort switch(SW1) */
+ SetIntMode(IV_GPIO(8), IM_ENA|IM_LEVEL|IM_HI);
+ EnableInt(IV_GPIO(8));
+
+ return E_OK;
+}
+
+/*
+ * Target system-dependent finalization
+ * Normally jump to ROM monitor.
+ * No return from this function.
+ */
+EXPORT void tkdev_exit( void )
+{
+ disint();
+ tm_exit(0); /* Turn off power and exit */
+
+ /* Not suppose to return from 'tm_exit,' but just in case */
+ for ( ;; ) {
+ tm_monitor(); /* To T-Monitor */
+ }
+}
diff --git a/tkernel_source/sysdepend/arm/mach-mx28/tkdev_timer.h b/tkernel_source/sysdepend/arm/mach-mx28/tkdev_timer.h
new file mode 100644
index 0000000..12b55a1
--- /dev/null
+++ b/tkernel_source/sysdepend/arm/mach-mx28/tkdev_timer.h
@@ -0,0 +1,185 @@
+/*
+ *----------------------------------------------------------------------
+ * T-Kernel 2.0 Software Package
+ *
+ * Copyright 2011 by Ken Sakamura.
+ * This software is distributed under the latest version of T-License 2.x.
+ *----------------------------------------------------------------------
+ *
+ * Released by T-Engine Forum(http://www.t-engine.org/) at 2011/05/17.
+ * Modified by TRON Forum(http://www.tron.org/) at 2015/06/01.
+ *
+ *----------------------------------------------------------------------
+ */
+
+/*
+ * tkdev_timer.h (EM1-D512)
+ * Hardware-Dependent Timer Processing
+ */
+
+#ifndef _TKDEV_TIMER_
+#define _TKDEV_TIMER_
+
+#include <tk/syslib.h>
+#include <sys/sysinfo.h>
+#include "tkdev_conf.h"
+
+/*
+ * Range of settable period (microseconds)
+ */
+#define MIN_TIMER_PERIOD 10
+#define MAX_TIMER_PERIOD 50000
+
+/*
+ * Setting up timer
+ */
+Inline void init_hw_timer( void )
+{
+ UW n, d, imask;
+
+ DI(imask);
+
+ /* stop timer */
+ out_w(TI_OP, 0);
+
+ /* choose clock */
+ out_w(TI0TIN_SEL, (in_w(TI0TIN_SEL) & ~3) | TITIN_PLL3);
+ d = in_w(DIVTIMTIN);
+
+ /* supply clock */
+ out_w(GCLKCTRL3ENA, in_w(GCLKCTRL3ENA) | TI0_TIN_GCK);
+ out_w(GCLKCTRL3, in_w(GCLKCTRL3) | TI0_TIN_GCK);
+
+ /* enable timer */
+ out_w(TI_OP, TM_EN);
+ while ( (in_w(TI_SCLR) & TM_SCLR) != 0 );
+ WaitUsec(100);
+
+ /* set counter */
+ n = (TIMER_PERIOD * TIN_CLK(d)) / 1000000 - 1;
+ out_w(TI_SET, n);
+
+ /* start timer count */
+ out_w(TI_OP, TO_EN|TSTART|TM_EN);
+
+ EI(imask);
+}
+
+/*
+ * Timer start processing
+ * Initialize timer, and start periodic timer interrupt.
+ */
+Inline void start_hw_timer( void )
+{
+IMPORT void timer_handler_startup( void );
+
+ /* set up timer */
+ init_hw_timer();
+
+ /* define interrupt handler */
+ define_inthdr(VECNO_TIMER, timer_handler_startup);
+
+ /* enable timer interrupt */
+ SetIntMode(VECNO_TIMER, IM_ENA);
+ ClearInt(VECNO_TIMER);
+ EnableInt(VECNO_TIMER);
+}
+
+/*
+ * Clear timer interrupt
+ * clear timer interrupt. Depending on hardware, we have to clear
+ * the request of the timer interrupt at the beginning of the
+ * timer handler, or clear it at the end.
+ * clear_hw_timer_interrupt() is called at the beginning of the
+ * timer interrupt handler.
+ * end_of_hw_timer_interrupt() is called at the end.
+ * Either one of them, or both are used according hardware requirements.
+ */
+Inline void clear_hw_timer_interrupt( void )
+{
+ /* Mask the current interrupt to allow multiple interrupts */
+ out_w(IT0_IDS1, IRQM(IRQ_TIMER));
+
+ /* Clear timer interrupt */
+ out_w(IT0_IIR, IRQM(IRQ_TIMER));
+}
+Inline void end_of_hw_timer_interrupt( void )
+{
+ /* Enable the current interrupt */
+ out_w(IT0_IEN1, IRQM(IRQ_TIMER));
+}
+
+/*
+ * Timer stop processing
+ * stop timer
+ * called during system shutdown
+ */
+Inline void terminate_hw_timer( void )
+{
+ UW imask;
+
+ /* disable timer interrupt */
+ DisableInt(VECNO_TIMER);
+
+ DI(imask);
+
+ /* stop timer */
+ out_w(TI_OP, 0);
+
+ /* stop clock */
+ out_w(GCLKCTRL3, in_w(GCLKCTRL3) & ~TI0_TIN_GCK);
+
+ EI(imask);
+}
+
+/*
+ * Obtain the elapsed time (nanoseconds) from the last timer interrupt
+ * To compensate for the possibility that the timer interrupt may have
+ * occurred during the interval when the interrupt was disabled,
+ * we calculate the time in the following range:
+ * 0 <= elapsed time < TIMER_PERIOD * 2
+ */
+Inline UINT get_hw_timer_nsec( void )
+{
+ UW ofs, max, ovf, imask, d;
+
+ DI(imask);
+
+ d = in_w(DIVTIMTIN);
+
+ max = in_w(TI_SET);
+ do {
+ ovf = in_w(IT0_RAW1) & IRQM(IRQ_TIMER);
+ ofs = in_w(TI_RCR);
+ } while ( ovf != (in_w(IT0_RAW1) & IRQM(IRQ_TIMER)) );
+ if ( ovf != 0 ) ofs += max + 1;
+
+ EI(imask);
+
+ return ofs * 1000000000LL / TIN_CLK(d);
+}
+
+/*
+ * Similar to the function as above, but returns value in microseconds.
+ */
+Inline UINT get_hw_timer_usec( void )
+{
+ UW ofs, max, ovf, imask, d;
+
+ DI(imask);
+
+ d = in_w(DIVTIMTIN);
+
+ max = in_w(TI_SET);
+ do {
+ ovf = in_w(IT0_RAW1) & IRQM(IRQ_TIMER);
+ ofs = in_w(TI_RCR);
+ } while ( ovf != (in_w(IT0_RAW1) & IRQM(IRQ_TIMER)) );
+ if ( ovf != 0 ) ofs += max + 1;
+
+ EI(imask);
+
+ return (ofs + 1) * 1000000LL / TIN_CLK(d);
+}
+
+#endif /* _TKDEV_TIMER_ */
--
1.9.1
