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[Bug 1295738]

 

Reverting this patch in 209897 bug still occurs in trunk with -mno-lra.

SPILL failure occurs for regno 110 ("dst" operand) in below instruction

(insn 634 633 635 27 (parallel [
            (set (reg:SI 3 r3)
                (ior:SI (eq:SI (reg/v:SI 110 [ dst ]) <== This operand r5 is registers gets assigned
                        (reg/v:SI 112 [ op2 ]))
                    (eq:SI (reg/v:SI 110 [ dst ]) <== This operand
                        (reg/v:SI 111 [ op1 ]))))
            (clobber (reg:CC 100 cc))
        ]) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:179 300 {*ior_scc_scc

First observation is that reload is not able to reuse "r5" that was used
in second reload in operation for the same register id 110 "dst"


The IRA Dump shows.
 
(insn 632 631 633 27 (set (reg:SI 1 r1)
        (reg/v:SI 110 [ dst ])) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:179 667 {*thumb2_movsi_vfp}
     (nil))
(insn 633 632 634 27 (set (reg:SI 2 r2)
        (const_int 0 [0])) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:179 667 {*thumb2_movsi_vfp}
     (nil))
(insn 634 633 635 27 (parallel [
            (set (reg:SI 3 r3)
                (ior:SI (eq:SI (reg/v:SI 110 [ dst ])
                        (reg/v:SI 112 [ op2 ]))
                    (eq:SI (reg/v:SI 110 [ dst ])
                        (reg/v:SI 111 [ op1 ]))))
            (clobber (reg:CC 100 cc))
        ]) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:179 300 {*ior_scc_scc}

The register operand 110 "dst" is already passed as argument 1 and hence
gets register r1. See insn 632.

But this is not reused by  insn 634.

However there are some other places in IRA dump where the same
expression occurs and there register r1 is used. Here operand "dst" 110
is marked as dead.


(insn 431 430 433 24 (set (reg:SI 1 r1)
        (reg/v:SI 110 [ dst ])) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:388 667 {*thumb2_movsi_vfp}
     (expr_list:REG_DEAD (reg/v:SI 110 [ dst ])
        (nil)))

(insn 433 431 432 24 (parallel [
            (set (reg:SI 3 r3)
                (ior:SI (eq:SI (reg/v:SI 112 [ op ])
                        (reg:SI 1 r1))
                    (eq:SI (reg/v:SI 111 [ op ])
                        (reg:SI 1 r1))))
            (clobber (reg:CC 100 cc))
        ]) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:388 300 {*ior_scc_scc 


Still working on why IRA is not replacing the operand with R1 here, but replaces in other places.

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https://bugs.launchpad.net/bugs/1295738

Title:
  [4.8 Regression] unable to find a register to spill in class 'LO_REGS'

Status in The GNU Compiler Collection:
  New
Status in Linaro GCC:
  Triaged
Status in gcc-4.8 package in Ubuntu:
  New

Bug description:
  seen with the 4.8 branch on arm-linux-gnueabihf, configured with
  --with-arch=armv7-a --with-fpu=vfpv3-d16 --with-float=hard --with-mode=thumb 

  omitting the -fno-tree-dce works around the issue.  not seen with the
  4.7 branch and trunk 20140306.

  $ g++ -std=c++11 -fPIC -fno-tree-dce -fno-exceptions -fno-omit-frame-pointer -c -g -O2 JITArithmetic32_64.ii
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp: In member function 'void JSC::JIT::emit_op_add(JSC::Instruction*)':
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:526:1: error: unable to find a register to spill in class 'LO_REGS'
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:526:1: error: this is the insn:
  (insn 335 334 336 20 (parallel [
              (set (reg:SI 3 r3)
                  (ior:SI (eq:SI (reg/v:SI 112 [ op ])
                          (reg/v:SI 110 [ dst ]))
                      (eq:SI (reg/v:SI 111 [ op ])
                          (reg/v:SI 110 [ dst ]))))
              (clobber (reg:CC 100 cc))
          ]) ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:514 295 {*ior_scc_scc}
       (expr_list:REG_UNUSED (reg:CC 100 cc)
          (nil)))
  ../Source/JavaScriptCore/jit/JITArithmetic32_64.cpp:526: confused by earlier errors, bailing out
  Preprocessed source stored into /tmp/ccb0Osgc.out file, please attach this to your bugreport.

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