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Re: Stability Under Load


Just to expand a little on the observed clock/voltage scaling:

216MHz -> 750mV
312MHz -> 750mV
456MHz -> 750mV
608MHz -> 825mV
760MHz -> 875mV
816MHz -> 875mV
912MHz -> 925mV
1000MHz -> 975mV

So it seems the voltage scaling values are not at all indexed in the same way as the clock speeds.

So either the code in tegra2_dvfs.c is very broken or there is something else very obscurely going on. I'm not prepared to discount either possibility. I'll take a look at the overclocking kernels of some of the Tegra2 based Android phones and see if I can acquire any insight from there.