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Re: PCBNEW: "Select Layer Pair for Vias" dialog


Dick H. a écrit :


This dialog gives the user a chance to select a pair of layers, yet
when you place a via, it ignores these layers and uses COPPER and
COMPONENT (unless you were savy enough to find the "via type" setting
in another dialog box).

This is terribly unfriendly, and it has cost me hours of work. I
placed many vias which should be copper to power, or component to
ground, etc. on my 4 layer board. Not copper to component.

Now, it seems there is no easy way to edit the type of via after it
has been placed. (Except for using a text editor on the brd file.)

Also, what if I want a via to conduct to 3 layers? I thought I could
place a 2nd via in the same place. But the user is prevented from
placing a second via in the same place, by line 186 of editrack-part2.cpp.

It would be nice to understand the reasoning behind some of this
behavior, if any. Then maybe I could help offer a solution.

the m_Layer parametre is the layer for tracks only.
for vias, m_Layer is the layer pair: an a via is on all layers from a starting layer to an ending layer
4 bits are for the starting layer and 4 bits are for the ending layer:
if m_Layer is 0x0F:
for a track, the meaning is : track is on layer 15 (component)
for a via, the meaning is : via is on all layers, FROM layer 0 (copper) TO layer 15 (component)

Vias "through" connect All layers (for pcbnew from copper to component layer, because copper is the layer 0 and component is the layer 15). And therefore the m_Layer param always is 0x0F ( or 0xF0 , which is equivalent) The layer pair choice allows you only to switch easily from a layer to the other layer for the tracks.
But vias are from layer 0 to layer 15 (from copper to component).

Only blind vias or buried vias must be from layer n to layer m (n and m = 0 ..15)

But blind vias or buried vias are experimental features, not really tested, and excellon files do not support them. (because only few manufacturers are able to made borads with these vias) and i don't made any board with thes vias.

You *** MUST *** have all yours vias with layer from 0 to 15 (m_Layer = 15).

Jean-Pierre CHARRAS
Maître de conférences
Directeur d'études 2ieme année.
Génie Electrique et Informatique Industrielle 2
Institut Universitaire de Technologie 1 de Grenoble
BP 67, 38402 St Martin d'Heres Cedex

Recherche :
Grenoble Image Parole Signal Automatique (GIPSA - INPG)
46, Avenue Félix Viallet
38031 Grenoble Cedex

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