kicad-developers team mailing list archive

["Frank Bennett" <bennett78@...>]

--- In kicad-devel@xxxxxxxxxxxxxxx, "daystar1013" <daystar@...> wrote:
>
> I think Tim has a valid point Dick. As a former Orcad user I 
> understand exactly what Tim is talking about. Orcad allows you to use 
> instances of sheets (instantiation) any number of times and each 
> instance has its own unique references.

Think of each sheet as a symbol which has a schematic for a part
or simply a duplicated circuit. In Verilog or other HDL languages 
an instance is "scoped" or resolved as sh1.U1, sh2.U1, etc or 
when the hierarchy netlist is flattened net pin (port) a slightly
different format: sh1_U1.1

74ls00 U1 {
.a1(signal_a),
.b1(input_b),
.y1(output);
}
74ls00 U2 {
.a1(output1),
.b1(input_c),
.y1(output2);
}

Here a port name (a1,b1,y1) is used instead of a pin#

We have an opportunity to improve over OrCad, which I don't
find useful for FPGA or ASIC schematic capture. TkGate is a good
example of a schematic capture/simulator that actually used Verilog
as it's input/output/netlist format with the graphic info embedded 
as comments.

A productivity feature missing from OrCad and tkGate is when
a pin is added to either the symbol or schematic sheet view it 
should automaticly show up in the other view, same name.

One problem in KiCad is that throughout, a pin number is allocated
with a fixed size of char[4] while as I recall the ref_designator 
is a *char. BGA packages have a 2 dimensional numbering scheme 
A1..Z99 (or is it A001..Z999?) which fit in a char[4] but a pin 
name of a general length would not....oh, well!

Merry Christmas,
-Frank
> 
> --- In kicad-devel@xxxxxxxxxxxxxxx, Dick Hollenbeck <dick@> wrote:
> >
> > Tim Hanson wrote:
> > > okok sorry. I'll try to state it another way. Perhaps I am doing 
> something
> > > wrong with sheets? (that the software already does? (i hope))
> > >
> > > Say I have two .sch files in my design. call them dsp and adc.
> > > one dsp hooks up to 4 adc sheets, hence there are 4 adc.sch 
> rectangles in
> > > dsp.sch
> > >
> > > I want to annotate (assign component references to) the 
> capacitors,
> > > integrated circuits and stuff in both .sch files. However, 
> one .sch file
> > > makes 4 sheets, so I cannot save the component references for all 
> of them.
> > >
> > > This means when I turn off my computer at night, start up the 
> next day, I
> > > have to re-annotate, otherwise there will be duplicated component
> > > references (read in from adc.sch). Now, if i re-annotate and am 
> partially
> > > done with a layout, everything will be all confused because the 
> component
> > > references will change in the schematic.
> > >
> > > Hypothetically, I can make a whole bunch of files, adc_1.sch 
> adc_2.sch 
> > > ...etc. Then have to edit each (of 16, in one case) if (when!) I 
> realize
> > > I've made a mistake. not elegant.
> > >   
> > Tim,
> > 
> > I think this option is what is intended by the current support.  
> (Not 
> > elegant, but functional.) However, since you are such a clever 
> guy and 
> > the files are all ascii text, you could write a shell script or 
> batch 
> > file to rename various aspects of your "source" schematics. You 
> could 
> > maintain your "source" file like schematics in un-annotated form, 
> and 
> > then have a script that copies that source file to unique names as 
> > needed by Kicad. Then annotate after they are all renamed and put 
> into 
> > place.
> > 
> > In the files area of one of the groups was a SED script I wrote to 
> > change all the fonts in a PCB file. Something like that could be 
> done 
> > to modify any part of the ascii SCH files as well.
> > 
> > What you are asking about is a Macro-like feature that seems not be 
> > present in eescema to my knowledge. But as I say, since these are 
> ascii 
> > files, you can build your own replication scheme using a scripting 
> > language of your choice, from a small set of "source" files.
> > 
> > Dick
> > 
> > 
> > 
> > > does this make sense??
> > >
> > > thanks for your input, and merry christmas!
> > >
> >
>