kicad-developers team mailing list archive

[Dick Hollenbeck <dick@xxxxxxxxxxx>]

>> What would the xml2ver converter do?  
>>     
> One use would be to get a Verilog netlist for a board schematic with 
> a number of ASIC/FPGAs to tie them together for simulation. Each ASIC/FPGA would 
> have it's own Verilog model and maybe reference a vendor library for logic/control.
> For RTL level simulation an option to include key schematic logic comments inline with
> the RTL library blocks maybe something like: 
>    "//ver: reg out;\n always @ posedge(ck) \n q <= in;\n"
>   

Not clear where that would go within eeschema, unless you can fit it
into a component field.  Can setup a "stock" fieldname using the
template fieldnames support.

>   
>> Have you looked at eeschema's XML export yet?
>>     
> Not yet. This weekend when I not working "contract Firmware". 
> Do lib module IO ports include any in,out,bidir attributes?
>   

No, please feel free to add them at

eeschema/netform.cpp's

   wxXmlNode* EXPORT_HELP::makeGenericLibParts()

line --> // caution: construction work site here, drive slowly

search for the above line.  Should be only a handful of lines of code.

Dick