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Re: BOM support


 Dick Hollenbeck wrote:
>> Frank,
>> I rushed out a shim that I wanted to get in there on top of wxXmlNode
>> called XNODE.  Please be advised that netform.cpp has recently changed. 
>> Grab a new snapshot if you have already gotten it.
> I'm going to punt on xml2ver:
>   o for RTL simulation a hierarchical netlist is desired. Each eeschema
> sheet would need to become a Verilog module- netlist per sheet,
> port names, no pins numbers.  EEschema drives to a flat netlist needed by
> pcbnew. An eeschema mode would have to be added to get a hierarchical
> netlist.
>   o I started a schematic as an example, saved it and now EEschema
> says it's not an EEschema file !?
>   o I think the amount of support required would be high.
>   o the demand for such a feature would be low. RTL designers mostly
> use vi or emacs. tkgate schematic/simulator outputs a verilog netlist
> with symbol (sheet) position/size saved as comments although the creator
> didn't appreciate the duality between sheet pin names and sheet
> hierarchical
> pins. EEschema goes in one direction with an import hier pins to the
> sheet
> symbol. an out of business product (Speedchart) did an awesum job of
> pushing
> port names up and down the hierarchy.
>  o lastly, I've been doing Firmware the last 3 years and don't have a need
> to design or verify RTL, still hoping to do a FPGA some day.
> If an XML representation ever makes sense for PCB check out my PCB123
> example in xml4pcb at sourceforge.
> Take care,
> -Frank Bennett

Thank you for at least finishing the conversation.  It would have been
only luck that something designed for one or two purposes could have
also served yet another.