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Re: SWEET pin_merge



The first several pages of the above are helpful to understand what verilog does
in terms of

a) module definition
b) module instantiation
c) wires

I'm still wondering, if we could make the bridge into s-expression syntax, that
there could not be some re-usable concepts, or parallels between:

1) our "sheet" and a verilog "module".

2) our "net" and a verilog "wire", although a verilog wire has local, module
specific scope.

If this gets any legs, perhaps a better name than sheet is available.  (If you
sheet on my schematic, I kill you.)

Whatever sheet with a better name is, it has symbolic "ports" or "pins", and
this then becomes a potential building block for yet a higher up client.

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