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Re: SWEET pin_merge


On 4/14/2011 11:01 AM, Dick Hollenbeck wrote:
> http://een.iust.ac.ir/profs/mirzakuchaki/Synthesis/Lectures-pdf/DigitalICdesignCourse_session03.pdf
> The first several pages of the above are helpful to understand what verilog does
> in terms of
> a) module definition
> b) module instantiation
> c) wires
> I'm still wondering, if we could make the bridge into s-expression syntax, that
> there could not be some re-usable concepts, or parallels between:
> 1) our "sheet" and a verilog "module".
> 2) our "net" and a verilog "wire", although a verilog wire has local, module
> specific scope.

I have no issues with borrowing someones ideas if we can't come up with a
better one ourselves.  The verilog abstraction levels are interesting but I'm
not sure how they would fit into the schematic sheet concept.

> If this gets any legs, perhaps a better name than sheet is available.  (If you
> sheet on my schematic, I kill you.)

Holy sheet Batman!  Feel free to insert your sheet here :)

> Whatever sheet with a better name is, it has symbolic "ports" or "pins", and
> this then becomes a potential building block for yet a higher up client.

Aren't sheets as we currently define them really just instances of a schematic
with hierarchical or global labels?  Why not treat them the same way we treat
parts in SWEET.  You could have a schematic that represents a functional block
(single NAND gate in SWEET), a group of functional blocks (7400 standard body
style definition in SWEET), or a complete stand alone design (complete 7400
with alternate body styles, foot prints, etc. in SWEET).  It seems to me there
are a lot of similarities between the two concepts.  Inheritance would work in
almost the same way with schematics as it does with parts.  Labels could be
remapped the same way pins are remapped and schematic properties could be
overridden just like SWEET.  You could even extend the part library source
concept for schematics.  Just food for thought.


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