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Re: [kicad-users] Re: Footprint with internal connection

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The problem is then that the pins do not match the vendor datasheet :/
Also, it does not work for PCBNEW (see attached demo schematic/board). PCBNEW's DRC still contains about unconnected pins. I guess we are at a stage where a kicad source change is unavoidable. 

cheers
  simon

On 08/25/2011 05:01 PM, Alain Mouette wrote:

I have allways solved this problem in a trivial maner:

1-----1
     |
      /
     |
2-----2

This way the schemaits remain simple and I can connect the pins in
whatever layer is best for any particular layout...

Alain

Em 24-08-2011 21:34, Jeff Barlow escreveu:

On 8/24/2011 5:20 PM, Simon Schubert wrote:

This is exactly my use case.  I have a small tactile switch, with the
vendor pinout being:

<http://industrial.panasonic.com/www-data/pdf/ATK0000/ATK0000CE6.pdf>

1-----3
       |
        /
       |
2-----4

IOW, 1 and 3 are connected interally, and 2 and 4 are.  Now, I can edit
the pad net of the module when it is on the board, but then KiCAD will
insist on a connection to that pad.  This is exactly the opposite of
what I want...  I want KiCAD to*know*  that pad 4 has the same net
connected as pad 2, automatically.  If that is not possible, maybe we
should add a way to do that?

An even simpler but equivalent case is a simple jumper or 0 ohm
resistor. The role of the part is to connect two nets into one. The
connected pins are interchangeable just like most passives. The DRC
should really recognize that the two nets are really one.

Attachment: test.brd
Description: application/vnd.cadsoft.eagle.board

Cmp-Mod V01 Created by CvPCB (2011-07-16 BZR 3051)-testing date = Thu 25 Aug 2011 11:13:10 PM CEST

BeginCmp
TimeStamp = /4E56BA66;
Reference = R1;
ValeurCmp = R;
IdModule  = R3;
EndCmp

BeginCmp
TimeStamp = /4E56BA63;
Reference = R2;
ValeurCmp = R;
IdModule  = test_connected_pins;
EndCmp

BeginCmp
TimeStamp = /4E56BA6D;
Reference = R3;
ValeurCmp = R;
IdModule  = R3;
EndCmp

BeginCmp
TimeStamp = /4E56BA7E;
Reference = R4;
ValeurCmp = R;
IdModule  = R3;
EndCmp

EndListe

# EESchema Netlist Version 1.1 created  Thu 25 Aug 2011 11:15:42 PM CEST
(
 ( /4E56BA7E $noname  R4 R {Lib=R}
  (    1 GND )
  (    2 N-000003 )
 )
 ( /4E56BA6D $noname  R3 R {Lib=R}
  (    1 GND )
  (    2 N-000002 )
 )
 ( /4E56BA66 $noname  R1 R {Lib=R}
  (    1 N-000003 )
  (    2 GND )
 )
 ( /4E56BA63 $noname  R2 R {Lib=R}
  (    1 N-000003 )
  (    2 N-000002 )
 )
)
*
{ Allowed footprints by component:
$component R4
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R3
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R1
 R?
 SM0603
 SM0805
 R?-*
$endlist
$component R2
 R?
 SM0603
 SM0805
 R?-*
$endlist
$endfootprintlist
}
{ Pin List by Nets
Net 1 "GND" "GND"
 R4 1
 R3 1
 R1 2
Net 2 "" ""
 R3 2
 R2 2
Net 3 "" ""
 R4 2
 R1 1
 R2 1
}
#End

update=Thu 25 Aug 2011 11:13:44 PM CEST
version=1
last_client=pcbnew
[cvpcb]
version=1
NetITyp=0
NetIExt=.net
PkgIExt=.pkg
NetDir=
LibDir=
NetType=0
[cvpcb/libraries]
EquName1=devcms
[eeschema]
version=1
LibDir=
NetFmt=1
HPGLSpd=20
HPGLDm=15
HPGLNum=1
offX_A4=0
offY_A4=0
offX_A3=0
offY_A3=0
offX_A2=0
offY_A2=0
offX_A1=0
offY_A1=0
offX_A0=0
offY_A0=0
offX_A=0
offY_A=0
offX_B=0
offY_B=0
offX_C=0
offY_C=0
offX_D=0
offY_D=0
offX_E=0
offY_E=0
RptD_X=0
RptD_Y=100
RptLab=1
SimCmd=
UseNetN=0
LabSize=60
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
[general]
version=1
[pcbnew]
version=1
PadDrlX=0
PadDimH=600
PadDimV=600
BoardThickness=630
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
LastNetListRead=test.net
[pcbnew/libraries]
LibDir=
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=test_connected_pins

Attachment: test.sch
Description: application/vnd.cadsoft.eagle.schematic

Attachment: test_connected_pins.mod
Description: audio/mod

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