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Re: Concerns about clearing disagreements before committing.



On Sat, 26 Nov 2011, Lorenzo Marcantonio wrote:

> On Sat, Nov 26, 2011 at 04:01:46AM -0700, Brian F. G. Bidulock wrote:
> Read the notes document. Interesting stuff I think that some of them
> belong to the CAM world more than to the CAD; but maybe our
> manufacturing reality are different: for example here there is no
> plot-to-go for more than 2 layers, even a plain 4 layer is fabricator
> revised!

Thank you for taking the time to read and comment on the document.

> My comments: the NSMD technology is useful not only for BGA (which I don't
> use:P) but for power SMD FETs too (these use pads that border on a zone
> fill:D). I think that's our background is most different: you work on high
> speed, I work on high power (50A per track and metal cores are not unusual
> here...)

Well, we are probably at domain extremes, which is in fact good.  Less
gets missed that way.  I often bridge zones with lumped decoupling
capacitors that require SMD on both ends.  BGA pads a just a slightly
more complex scenario.

> Teardrops an T-joins could be useful directly in the CAD, too, since they are
> not process dependant. Track chamfering and mitering could be useful in
> controlled impedance routing too (I have little experience with that, sorry,
> our idea of *funny* tracks are 180um thick, 20mm wide ones --- there are
> fabricators which do 6mm thick copper :D).
> Unsupported and non-functional pad removal was one of the reason for which I
> called for a copper mask for vias and pads (along with other DRC which you
> righly requested).

Well, I wasn't really requesting: I was writing requirements for my own
coding work.

> Regarding complex pad shapes: aperture macros could be actually useful; the
> problem is identifying the common subset: I never used DPF but, maybe, there
> are some gerber features not available elsewhere and so on. In fact one of our
> fabricator simply reject a gerber using AM for drawing thermals!

Sounds like we need a checkbox there...  Thanks for pointing that out.

> Maybe their CAM didn't support them correctly, I don't know. Anyway
> using multiple pads for representing the drain of, say, a DirectFET
> drain is a PITA (you need to connect all of them with bonding tracks
> *avoiding* cooling vias to satisfy pcbnew DRC). BTW I have no idea of
> what the moire pattern could be used for except for thermals:P
> For this I think that the module format *must* be changed... if it's backward
> compatible in reading I see no problem with that. Just add two new elements for
> the 'aperture macro' and 'macro pad' and you're set, the euristics about
> joining the same numbered pads IMHO are too complex and there's risk of d-code
> number explosion; explicitly declaring a macro usage also would make easier to
> maintain the module.

Good point.  I agree.  I was changing so much that I initially tried to
avoid changing things such as the module editor wherever possible.

> Comment about drill mark plotting (similar to the avoidance of AM for
> thermals): some fabricators don't accept composite layers; you need a negative
> subimage for drill marks and that would be rejected. At least I think everybody
> now accepts polygonal fills, so we can junk the raster filled zones, at least.

There is an existing drill marks check box on the Gerber plot dialog.
Uncheck it an there will be no scratch layers.  As regards polygon
fills, many fabricators say that they do no want stroked zones.

> Fiducial marks: in your country maybe you use SMEMA marks, our board marks are
> different: circular 1mm pad, 2mm square mask *and* solder paste on the pad.
> Don't ask me why, here in italy it seems to be the standard! I treat board
> fiducials as modules, and local fiducials (when needed) as pads; a flag in the
> pad structure could be useful maybe ("this is a fiducial").

Actually that is a SMEMA compliant mark.  The mask does not have to be
circular, it just needs to have a aperture that is at least the circular
area (which the square satisfies).

> BTW how are bad fiducial used? they scratch them when a board is bad?
> bad boards in our panel are simply marked with a blob of paint:P

Yes, they score them out when a single board in a assembly panel array is bad.
> Some feature requested, especially paneling, are clearly *not* belonging to a
> CAD system... these are too dependant on the fabrication process. In fact, when
> you have multiple board fabricator, you don't even enlarge solder mask, because
> each of them has its rules concerning clearance and registration! Maybe
> fabricators for ultrahighspeed boards are more specific in their specifications
> but usually we're lucky if the copper deposit thickness is right:P:P Anyway I
> concur that for board simulation you'll need to handle the track profile. Good
> luck in finding the etchin parameters.  Etch compensation IMHO pertain
> to a CAM system, not to kicad.

Being somewhat off on the etch factor is not a big issue to the
calculation.  Not applying it at all is a big deal.  A reasonable
default value will do in many cases.

> I'm a supporter of the unix philosophy: one program for one thing;
> design with kicad, postprocess for fabrication with something else.
> Otherwise we risk a bloaty beast. 

The problem with that approach that you result with a design tool that
eagerly creates boards that are impossible to fabricate or assemble.
Not performing DFX or DFM during design is an inferior way of doing

> Isolation traces: I don't know about high speed design but I've been taught
> that 'dead copper is bad'. When I do them I connect them to the appropriate
> 'shield potential'. It's not strange to have four or five different 'ground
> potentials' on a board (and joining them is tricky). Anyway just handle them as
> connected to some special net i.e. the disconnected net. And of course the same
> is for isolation zones; question: could be some unrelated isolation so near to
> be confused and so joined together? maybe just one isolation net is not enough.

PCBNEW traces get their network number from pads to which they are connected.
Zones can be assigned net names, but I noticed that if there are never
connected ultimately to pads, they tend to lose their networks numbers
when the board is closed and reopened.

> Arced tracks and neck downs: useful, I agree (never had the need for an arced
> track, beside).

Signal integrity.  Meandering of high-speed traces can also be tighter
when the track segments of the meander are arced.  It also improvides
yeilds on narrow traces by avoiding blossoming chemistry and effects at
sharp interior and exterior corners.

> Push-pull track: woot, the wondrous push/shove router:D:D Me want it:D

I roughed it out, it should not be that hard with the proximity maps
quickly determining what might be able to be pushed or what could be

> Solder dams, mask ganging and so one are strictly a CAM issue and shouldn't
> belong to kicad. 

Acutally, it is not a CAM issue to me, it is a cost issue.  If I don't
solve the issue in the artwork, the fabricator will manually apply them
at a cost per site per board.  To avoid that cost, they nicely describe
how to go about doing it on the artwork yourself.

> Embedded resistors: these could be used for thick film surface resistors, too!
> Not laminated but dispensed, anyway the process is similar. No idea about the
> computation, tough.

I don't think that resistance layers can handle anywhere near the
wattage that you are talking about.  I think that they only handle 1/8W
or even less, but I might be wrong.

> Venting/thieving: let them to the fabricator. An indication on where
> vent/thieve can be useful (to avoid risking your precious ground shield:P).

My major reason for wanting this is to calculate more accurately the
press factor to determine finished dielectric thickness for impedance
and heat transfer calculations.  But, others on the list requested it.

> Coupons: strictly fabrication features. Don't below to kicad since they depends
> on *both* the fabricator and the assembler.

Perhaps you are thinking fabrication coupons that goin the in fab rails
of the panel.  Impeadance coupons must be supplied on high speed boards
that require controlled impedance.

> I read about your 'one tool to bind them all' section. Sorry, this industry
> just don't work this way. You *have* to work with fabricators and assemblers.
> One times we had to move a fiducials due to constraints in the pick and place
> optics. Even if you send them enlarged masks they junk it and redo them (or at
> least reject the production). As a board designer do your work, and let them do
> their. Do you think you could know *all* of the quirks of their equipment? If
> you need some specific guarantee (i.e. pressing tolerances) put them in written
> on the fabrication layer and then send back the boards as defective if they
> don't match. Design conservatively (i.e. try to absorb manufacturing tolerances)
> If you have multiple suppliers of course it's even more difficult than that.

I was waxing lyrical at that point.  What I want is a CAD system that
helps me design a board that can be fabricated and assembled more than
it helps me design one that can't.

> > The Eco, Comment and Drawing layers are simply as before.  Comment layer
> I mean, not the layer name, but the layer *behaviour*. They all are simply
> artwork layers. Same class different instance. 
> > 258X expects the layer classes as laid out (except Eco and Comment).
> > I didn't invent them.
> Sorry, I don't know about 258X
> > Another example, SolderPaste is not just a "pad-master", it is the solder
> > paste stencil apertures, complete with stencil thickness considerations,
> > bow-ties, D-shapes or homeplates; consideration for TFN and CGBA; paste
> > in hole, etc.
> Good luck on this, stencil are cut in a myriad of ways and every
> fabricator has its own rules.  *They* need to fix stencil, you only
> need to tell them where the paste has to be put and how much of it.
> Laser cut, electroerosion or even paste dispensing... it's even
> different if paste is hand applied or machine applied, these are
> differences the designer can't cope with (because simply doesn't know)

Board fabricators do not cut stencils.  Assemblers do.  For prototypes I
am the assembler.  I need my stencils cut by the stencil cutter to my
specifications.  I do not wish to write another program with another gui
and another file format and another set of portability problems to add
one dialog and 20 lines of calculation to a plot routine.  For short run
I need to know that one stencil thickness will do, otherwise the cost
can skyrocket.

> > Contacts is for edge fingers, carbon contacts, tie bars for plating lines,
> > etc.  These have additional rules so that they can be dipped or carbon
> > deposit masks generated.
> These also are manufacturing rules. Do you know the specifics of your
> manufacturer process?

Yes.  They told me in their published DFM guidelines.

> > I already did Lavenir Format 2 (IPC-D-356) Lavenir Format 4 (IPC-D-356
> > with NTD), IPC-D-356A and IPC-D-356B.  Also Barco DPF with netlist,
> > Gencad, Gencam (IPC-2511A), GenCAM-XML (IPC-2411B) and 258X (IPC-2851).
> I missed 356B... what's new regarding 356A?

NTD in same file.

> > I also provided several classes of layer-sets.  Layersets are groups
> > of substrate and copper in a buildup.  Layer set classes include:
> > 
> >   Laminate:- press cycle buildups.
> >   Pth:- plate through holes (not necessarily through entire board, but
> > 	through sub-lamminate).
> >   Dcd:- Depth controlled drilling of outer layers of sublaminate.
> >   HoleFill:- Hole filling from outer layers of sublaminate.
> >   Laser:- Laser drilling from outer layers of sublaminate.
> >   Backdrill:- Backdrilling of Pth for sublaminate.
> >   Npth:- Non-plate-through holes in sublaminate.
> >   Route:- edges, slots, wells, cutouts in sublaminate.
> As before some of these are manufacturer dependant and don't belong to
> the cad: what about if the manufacturers prefer to laser drill (say)
> the 0,3 mm holes which you tought were mechanically drilled?  just ask
> for the holes (finished hole *and* inner plating if needed), let them
> do their work and adjust for their process.

Quite the contrary.  These processes place specific requirements on
the design data set (type, number and contents of excellon drill files).
Also, clearance pads and clearance holes must be applied or not applied
based on the approach to making the hole.  Also, things like Pth vs. Npth
are design issues not manufacturing issues.

Thank you again very much for your comments.


Brian F. G. Bidulock    � The reasonable man adapts himself to the �
bidulock@xxxxxxxxxxx    � world; the unreasonable one persists in  �
http://www.openss7.org/ � trying  to adapt the  world  to himself. �
                        � Therefore  all  progress  depends on the �
                        � unreasonable man. -- George Bernard Shaw �