kicad-developers team mailing list archive

[Dan Chianucci <trump211dev@xxxxxxxxx>]

On Apr 19, 2012 5:27 PM, "Dick Hollenbeck" <dick@xxxxxxxxxxx> wrote:
>
> On 04/19/2012 05:22 AM, Solonen Vesa wrote:
> >> I am trying to add this functionality, however I am unsure how to go
about it.
> > For zone stitching it may make sense to use our current zone filling
logic for the purpose. If you look carefully you see zones are filled with
polygons and their edges are "rounded" with a track defining also the
minimum fill width. That edge track could be used for automatic via
stitching with a bit of additional logic how to place vias and how to
handle the length of stitching if all the edges are not stitched.
> >
> > -Vesa
> >
>
>
> My understanding is that this may already work, provided that you:
>
>
> a) tie the vias together with a track, and
> b) are willing to ignore some DRC errors.
>

You are correct, however, you have to tie that track eventually to a pad
with the same net.  The problem was that in the function
PCB_BASE_FRAME::RecalculateAllTracksNetcode()
In order to Keep track of which tracks had already been visited, it set all
of the net-codes to 0.  However, after the net-code reset, only tracks that
were somewhere connected to a pad
had there real netcode reinstantiated.  Since the vias in the middle of the
zones werent connected by another track to a pad, there netcodes never
changed back from 0, and there fore
the Zone wouldn't connect to them

> This suggests that the filling portion is probably solid already, and
there is some
> conditional logic that needs re-working.
>
>
> I see the DRC errors on thermal pads, but I am currently ignoring them.
 I think for
> zones, the DRC thing may not be a problem, you just have to tie the via
together?

With this patch, DRC recognizes that the vias are connected, and doesn't
complain at all about them.

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