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Re: Feature bounties or Kickstarter project for KiCad


On 03/17/13 02:06, Dick Hollenbeck wrote:
> On 03/16/2013 07:52 AM, Vesa Solonen wrote:

>> * Differential netclass rules (potential classes)
>> * Differential line support
>> [* Finishing up KiCad-gal]

> I wonder if a written specification of the work (resultant features)
> might allow it to be measured by candidate developer(s) sufficiently
> well to actually bid on it.
> Although there may be a temptation to simply say something like "just
> like Altium", that may not be familiar to somebody.

I wish someone with more knowledge about the subject could explain how
established tools do it. I haven't used any other EDA tools than
CircuitMaker 2000 in the beginning of the millennia, some Eagle, gEDA
and KiCad. All of the use has been in the semiprofessional league. I
even got paid for layouts, but not every month.

Before jumping completely to KiCad ~2008 I haven't even needed such
functionality. I remember that Traxmaker in the previously mentioned
package was really painful to use for any layouts with copper pours
though. KiCad is really smooth these days and preimplementation of some
details regarding copper pours has been my patch contribution to KiCad
in the past. I wanted working oval and round thermals.

My first cut idea of the potential classes follows:

Every net has a general design rule that defines a minimum clearance
etc. Potential classes would be implemented by giving potential range
numbers to the net, and these rules must also be definable towards a
group of nets. These potential numbers would be used for clearances
between the nets, because not all of them are equal like in the current
DRC system.

There must also be a way for defining these in the schematic UI, because
with complex designs PCB phase is too complicated to track everything
properly. The way for splitting a net to say "contol" and "power" sides
must also be available.

The classical example of half-bridge circuit for the potential classes
functionality can be found in almost every SMPS layout:

HV––[power, 400]–––––––––––––––––––––––––––––––––
HG––[control, 0-415, 15 towards OUT and HS]–––>|=
HS––[control, 0-400]––––––––––––––––––––––––––––––––[power, 0-400]––OUT
LG––[control, 0-15]–––––––––––––––––––––––––––>|=
LS––[control, 0]–––––––––––––––––––––––––––––––––
PGND––[power, 0]–––––––––––––––––––––––––––––––––

Control and power split is at the T- and X-junctions towards the control
side. Clearances: small between [PGND, LS, LG] and between [HS, HG,
OUT], large between [HV, OUT, everything else]...

Implementing this DRC and automation feature would allow painless usage
of KiCad for power layouts. Currently it needs switching off the DRC and
making any adjustments afterwards is very error prone. Failing the
UL-test because of the 100um layout error can be costly too. Also making
the tool a bit smarter would allow separating the layout person and
schematic design person. Maybe not completely, but most of the
information would be automatically conveyed within the design files.


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