kicad-developers team mailing list archive

[Andrew Zonenberg <azonenberg@xxxxxxxxxxxxxxx>]

Please see attached patch. It works on all of my test cases and
generates one Excellon file for each pair of layers that have
buried/blind vias.

On Sat, 2014-07-19 at 21:20 -0400, Andrew Zonenberg wrote:
> UPDATE: Reading dialog_gendrill.cpp it seems that code which was
> intended to do this is present, but completely broken. I've partially
> fixed it (it now generates a drill file for each layer pair that has
> vias on it, but blind/buried vias also are plotted in the PTH drill
> file) and will be posting a patch once I've debugged a bit further.
> 
> On Sat, 2014-07-19 at 20:40 -0400, Andrew Zonenberg wrote:
> > I'm about to start work on a board that will have an 0.4mm BGA on it and
> > it seems that while current kicad supports editing blind/buried vias
> > there's no support for generation of sane drill files (one file per
> > layer pair).
> > 
> > I'm not really that familiar with the source structure of pcbnew, does
> > anyone have any idea where I should start looking? I want to modify the
> > "export drill file" code to create multiple drill files from the base
> > filename as follows:
> > 
> > foo.drl (through-board plated holes)
> > foo-npth.drl (through-board unplated holes)
> > foo-1-2.drl (blind vias from front to inner1)
> > foo-2-3.drl (buried vias from inner1 to inner2)
> > etc.
> > 
> > It'd probably be fairly simple to add a filter to the export code to say
> > "only put vias between these layers in this drill file" and then call
> > that function for each pair of layers.
> > 
> > _______________________________________________
> > Mailing list: https://launchpad.net/~kicad-developers
> > Post to     : kicad-developers@xxxxxxxxxxxxxxxxxxx
> > Unsubscribe : https://launchpad.net/~kicad-developers
> > More help   : https://help.launchpad.net/ListHelp
> 
> _______________________________________________
> Mailing list: https://launchpad.net/~kicad-developers
> Post to     : kicad-developers@xxxxxxxxxxxxxxxxxxx
> Unsubscribe : https://launchpad.net/~kicad-developers
> More help   : https://help.launchpad.net/ListHelp

-- 
Andrew Zonenberg
PhD student, security group
Computer Science Department
Rensselaer Polytechnic Institute
http://colossus.cs.rpi.edu/~azonenberg/

=== modified file 'pcbnew/dialogs/dialog_gendrill.cpp'
--- pcbnew/dialogs/dialog_gendrill.cpp	2014-06-24 16:17:18 +0000
+++ pcbnew/dialogs/dialog_gendrill.cpp	2014-07-20 01:46:10 +0000
@@ -361,8 +361,8 @@
     bool       hasBuriedVias = false;  /* If true, drill files are created
                                         * layer pair by layer pair for
                                         * buried vias */
-    int        layer1 = B_Cu;
-    int        layer2 = F_Cu;
+    int        layer1 = F_Cu;
+    int        layer2 = B_Cu;
     bool       gen_through_holes = true;
     bool       gen_NPTH_holes    = false;
 
@@ -400,14 +400,14 @@
             }
             else if( !gen_through_holes )
             {
-                if( layer1 == B_Cu )
+				if( layer1 == F_Cu )
+                    layer_extend << wxT( "-front" );
+                else
+                    layer_extend << wxT( "-inner" ) << layer1;
+				
+                if( layer2 == B_Cu )
                     layer_extend << wxT( "-back" );
                 else
-                    layer_extend << wxT( "-inner" ) << layer1;
-
-                if( layer2 == F_Cu )
-                    layer_extend << wxT( "-front" );
-                else
                     layer_extend << wxT( "-inner" ) << layer2;
             }
 
@@ -469,13 +469,13 @@
         else
         {
             if(  gen_through_holes )
-                layer2 = layer1 + 1;    // prepare generation of first layer pair
+                layer2 = layer1 + 1;    // done with through-board holes, prepare generation of first layer pair
             else
             {
-                if( layer2 >= F_Cu )    // no more layer pair to consider
+                if( layer2 >= B_Cu )    // no more layer pair to consider
                 {
-                    layer1 = B_Cu;
-                    layer2 = F_Cu;
+                    layer1 = F_Cu;
+                    layer2 = B_Cu;
                     gen_NPTH_holes = true;
                     continue;
                 }
@@ -484,8 +484,8 @@
                 layer2++;                      // use next layer pair
 
                 if( layer2 == m_parent->GetBoard()->GetCopperLayerCount() - 1 )
-                    layer2 = F_Cu;         // the last layer is always the
-                                                    // Front layer
+                    layer2 = B_Cu;         // the last layer is always the
+                                                    // back layer
             }
 
             gen_through_holes = false;

=== modified file 'pcbnew/exporters/gendrill_Excellon_writer.cpp'
--- pcbnew/exporters/gendrill_Excellon_writer.cpp	2014-07-02 07:05:29 +0000
+++ pcbnew/exporters/gendrill_Excellon_writer.cpp	2014-07-20 01:46:03 +0000
@@ -481,7 +481,12 @@
             if( aExcludeThroughHoles  && (new_hole.m_Hole_Bottom_Layer == B_Cu)
                && (new_hole.m_Hole_Top_Layer == F_Cu) )
                 continue;
-
+                
+            //If we're checking for through-hole vias, exclude all blind/buried ones
+            if( ( (aFirstLayer == F_Cu) && (aLastLayer == B_Cu) ) &&
+                ( (new_hole.m_Hole_Top_Layer != F_Cu) || (new_hole.m_Hole_Bottom_Layer != B_Cu) ) )
+                continue;
+	
             m_holeListBuffer.push_back( new_hole );
         }
     }

Attachment: signature.asc
Description: This is a digitally signed message part