| Thread Previous • Date Previous • Date Next • Thread Next |
After a discussion with Nick Oestergard on IRC, I've come to the conclusion that we really need to sit back and think about how design rules for vias and stackups are handled. As of right now, we have three kinds of vias: 1) Through-board via. These penetrate the entire board and can connect any layers in between. 2) Microvia. These can only go from an outer layer to the adjacent internal layer. 3) Blind/buried via. These go from any layer to any other layer, and can connect anything in between. We currently have two sets of design rules: 1) Drilled vias. There is a global minimum, netclass default size, and a list of custom sizes. This applies to both through and blind/buried vias. 2) Microvias. There is a global minimum, netclass default size, but no support for custom sizes. Unfortunately, this doesn't accurately reflect the realities of PCB manufacture. Mechanical drills can be done through the entire stack at any point during manufacture (including before all layers have been laminated), and laser drills can be done from any layer to the next one down (including before all layers have been laminated). Furthermore, minimum diameters of drills are typically limited by aspect ratio concerns. In other words, the less depth a drill has to penetrate, the smaller the hole can be. To illustrate my point, I've attached a cross section of a typical 6-layer HDI stackup (similar, but not identical, to one that I used on a project for work recently). There are quite a few different kinds of vias: 1) Buried mechanical drills from layer 3 to 4, through the board core before any prepregs are applied. These can be slightly smaller than through-board mechanical drills since the stack is thinner. 2) Buried laser drills from layer 2 to 3, the first level of prepreg, before the outer layer is laminated. These can be very tiny since they're only penetrating one layer. 3) Blind laser drills from layer 1 to 2, the second level of prepreg, after the stack is fully laminated. These can be just as small as the buried laser drills. 4) Mechanical drills through the entire board after the stack is fully laminated. These are the largest since they have to penetrate the entire stack. 5) Laser drills on the back side (4-5 or 5-6) are not allowed at all since this requires an extra process step, increases cost, and I only had fine-pitch BGAs on the front side of the board. Kicad's current model cannot handle this case well. I could use "microvias" from 1-2, but the 2-3 vias need to be "blind/buried", which uses the global through-board drill design rule. This means that I need to set the global drill minimum to something tiny like 6 mils, which would implicitly allow a 6 mil through-board mechanical drill (something few fabs can manufacture at all, and certainly not for a reasonable price). I also would need to enable blind/buried vias globally, which would allow me to do a 4-5 or 5-6 laser via accidentally and not catch it until I exported CAM files for manufacture. I think what we really need to do is define a more complete stackup editor that specifies layer thicknesses (for future impedance control/current capacity calculations etc), dielectric constants, and allows a list of layer pairs and via sizes to be defined. Does anyone have input into how this should work? I'm pretty busy but would like to at least get a non-functional mockup of the UI prototyped soon. For extra fun in the longer term, integrate with the PCB calculator so you can design design rules for target impedances. For example: Layer | Width | Spacing | Type | Z0 target | Z0 actual | F_Cu | 0.15 | | Single | 50.00 | 48.95 | F_Cu | 0.25 | 0.125 | Diff | 100.00 | 101.32 | In1_Cu | 0.125 | | Single | 50.00 | 51.24 | Then just select "50 ohm single" from the track width dropdown and the correct size for the current layer will be used automatically. -- Andrew Zonenberg PhD student, security group Computer Science Department Rensselaer Polytechnic Institute http://colossus.cs.rpi.edu/~azonenberg/
Attachment:
6l-stackup.png
Description: PNG image
Attachment:
signature.asc
Description: This is a digitally signed message part
| Thread Previous • Date Previous • Date Next • Thread Next |
