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Re: Discussion: Hidden Pins, Net labels

 

Hello, Simon!

There are lots of things possible:

On 2016-02-11 15:19, Simon Richter wrote:
> 5. Allow multiple pin definitions in a single device
> 6. Add generated symbols for ICs
> 7. Add tabular pin connections
> 8. Add pin and unit swap hints

but I am not sure how much of these should be implemented right in
schematics level or if it makes more sense to use a framework to
dynamically (re-)generate complex components when there are
changes.

Example: Look at the pin multiplexing functions of a still
small i.e. NXP i.MX287 ARM Application Processor.
One pin can have up to eight different configurations.
Peripheral Blocks can be mapped to different IOs in
a redundant fashion.
This gets so complex that they created a piece of software
(PinMux Tool) so be able to map all the IOs of these
CPUs resolving conflicts semi-automatically.

So, I am really not sure how much flexibility as well as
intelligence might be needed to do that on schematics
level. This (esp. 5.) looks like a "Fass ohne Boden" to
implement (==money sink, bottomless pit?).

It seems like big tool vendors tend to move towards
table-based entry and import functions for complex
components, so you can re-arrange and -assemble your
schematic symbols as you need them.

Regards,

Clemens


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